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2022-10-18serial: ns16550: support a list of clkyanhong.wang1-0/+12
Add a list of clk enable operation. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:starfive-jh7110: Modify the default division factor of sdcard clkyanhong.wang2-0/+9
Modify the default division factor of sdcard clk to 4. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: add usb init configyanhong.wang3-24/+84
Add usb init config for starfive EVB board. Default set to USB2.0 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang2-24/+4
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: change tx delay configyanhong.wang1-1/+1
Modify the tx delay configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18spl: satrfive: bus_root switch to pll2.samin2-9/+0
High-speed emmc/sdio support Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18spl:gpio: Set GPIO domain0-3 voltage to 1.8Vsamin1-1/+1
The default GPIO domian0-3 voltage is 3.3V, which is controlled by 4 bits. 0 means 3.3.V, 1 means 1.8V. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18board:starfive:evb: modify the GPIO configuration for sd moduleyanhong.wang3-9/+20
Modify the GPIO configuration for sd&emmc module, switch the clk of sd&emmc to high frequency Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: Modify sd node configurationyanhong.wang4-38/+7
Modify SD&EMMC node configuration on Starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:riscv:starfive-jh7110: Adjust CPU working frequencyyanhong.wang3-2/+52
Adjust CPU working frequency from 1G to 1.25G for starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18config:starfive-jh7110: add MICREL phy config to defconfigyanhong.wang1-0/+3
Add MICREL phy config to defconfig for starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: enable prefetcher and add two macaddress configurationyanhong.wang1-6/+10
Add two macaddress for gmac0 and gmac1. Enable prefetcher for EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: add ethernet-phy delay_chain configyanhong.wang2-4/+17
Add ethernet-phy delay_chain configuration for gmac1 on starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: add JH7110_GMAC1_GTXC clkyanhong.wang1-0/+4
Add JH7110_GMAC1_GTXC clk for GMAC1 on JH7110 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:dwc_eth_qos:starfive: remove phy-reset-gpio setyanhong.wang1-18/+1
Phy-reset-gpio set is unused in JH7110 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: Modify dynamic alloc memory start addr in SPLyanhong.wang1-3/+2
Modify the dynamic alloc memory start address from L2 LIM to DDR. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:starfive-jh7110: clear L2 LIM memoryyanhong.wang1-0/+14
Clear L2 LIM memory on StarFive JH7110, avoid some unexpect exception.
2022-10-18config:starfive-jh7110: update starfive evb board default configyanhong.wang1-0/+8
Add DDR config to the default config for starfive evb board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: add ddr device nodeyanhong.wang1-0/+7
Add ddr device node for JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add clk inityanhong.wang3-30/+58
Add clk init for ddr on JH7110 board Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: add ddr driveryanhong.wang10-0/+3203
Add driver for JH7110 to support ddr initialization in SPL. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com> Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18net: dwc_eth_qos:starfive: update clk inityanhong.wang1-96/+23
Modify the clk init code for StarFive JH7110 platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang3-6/+29
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add delay chainyanhong.wang1-12/+26
Add tx/rx delay chain for YUTAI 8521 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add macro definitionyanhong.wang1-0/+21
Add macro definition of GPIO Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive evb board supportyanhong.wang12-0/+734
Add board support for StarFive EVB. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Adjust the dependency of CLK_JH7110 & SPL_CLK_JH7110 macrosyanhong.wang1-2/+2
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive-jh7110: Adjust the dependency of RESET_JH7110 macroyanhong.wang1-1/+1
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang3-157/+496
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: remove unused clkyanhong.wang1-52/+4
Remove unused clock in order to reduce code size. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add YT8511/yt8521 phy inityanhong.wang1-0/+3
Add phy init for YUTAI YT8511/YT8521. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add YT8511/yt8521 phy driveryanhong.wang4-0/+293
This adds basic support for YUTAI YT8511/YT8521 phy. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18usb:cdns3:Add StarFive wrapper driver for CDNS USB3 controlleryanhong.wang3-0/+88
Add driver to handle StarFive specific wrapper for Cadence USB3 controller present on JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-53/+182
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive: Adjust judgment conditionsyanhong.wang1-4/+5
The serial driver will call reset driver, udelay function will be called in reset driver, but the timer is not init,so udelay function call will cases error. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add rtc timer inityanhong.wang2-1/+53
The rtc timer is used early in kernel, but the clk&reset driver is not ready,so some clk&reset init is placed here. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18script: add execute permissionyanhong.wang0-0/+0
Add executable permissions for script files. /*do not upstream*/ Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18config:starfive-jh7110: add config file for jh7110yanhong.wang1-0/+75
Add basic config option for StarFive VisionFive board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy: add 10/100M register configurationyanhong.wang2-0/+14
Support 10/100M configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive visionfive board supportyanhong.wang8-0/+518
Add board support for StarFive VisionFive. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net: dwc_eth_qos:starfive: add jh7110 supportyanhong.wang2-0/+290
Add new configuration for jh7110 soc platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: add jh7110 supportyanhong.wang6-0/+1341
Add dts support for jh7110. The starfive visionfive support is based on jh7110 soc. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18mtd:spi-nor-ids: Add support for GD25LQ256Dyanhong.wang2-0/+6
Adds support for GigaDevice's spi nor flash Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:soc:jh7110: Add support jh7110 soc.yanhong.wang7-0/+180
Add StarFive JH7110 soc to support RISC-V arch Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Add clock driver for JH7110yanhong.wang7-0/+1167
Add a clock driver for StarFive JH7110 Soc platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18misc:OTP:Starfive-jh7110: Add driver for the Starfive otp controlleryanhong.wang3-0/+196
Added a misc driver to handle OTP memory in Starfive SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add GPIO driver for JH7110yanhong.wang4-0/+224
Support for GPIO controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18Reset:Starfive-jh7110: Add reset driver for JH7110yanhong.wang4-0/+472
Support for reset controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-10-04Prepare v2021.10Tom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-04mtd: cqspi: Fix division by zeroMarek Vasut1-0/+3
Both dummy.nbytes and dummy.buswidth may be zero. By not checking the later, it is possible to trigger division by zero and a crash. This does happen with tiny SPI NOR framework in SPL. Fix this by adding the check and returning zero dummy bytes in such a case. Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Pratyush Yadav <p.yadav@ti.com> [trini: Drop Pratyush's RB as his requested changes weren't made as Marek disagreed]
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