diff options
| -rw-r--r-- | arch/riscv/dts/dubhe83_fpga-u-boot.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/riscv/dts/dubhe83_fpga-u-boot.dtsi b/arch/riscv/dts/dubhe83_fpga-u-boot.dtsi new file mode 100644 index 0000000000..155877fe34 --- /dev/null +++ b/arch/riscv/dts/dubhe83_fpga-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024 StarFive Technology Co., Ltd. */ + +#include "dubhe_fpga_common-u-boot.dtsi" + +&cpu0 { + riscv,isa = "rv64imafdchv_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicclsm_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_smstateen_svinval_svnapot_sscofpmf_sstc_zvbb_zvbc_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh"; +}; + +&cpu1 { + riscv,isa = "rv64imafdchv_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicclsm_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_smstateen_svinval_svnapot_sscofpmf_sstc_zvbb_zvbc_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh"; +}; + +&cpu2 { + riscv,isa = "rv64imafdchv_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicclsm_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_smstateen_svinval_svnapot_sscofpmf_sstc_zvbb_zvbc_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh"; +}; + +&cpu3 { + riscv,isa = "rv64imafdchv_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicclsm_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_smstateen_svinval_svnapot_sscofpmf_sstc_zvbb_zvbc_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh"; +}; |