diff options
| author | Oliver Chen <Oliver.Chen@nxp.com> | 2020-04-21 09:48:09 +0300 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-07-14 10:23:46 +0300 |
| commit | b335966958a93e49439bf248adadce89e7e2bee3 (patch) | |
| tree | d4ee266783df9801705bb751710514be758da202 /drivers/ddr/imx/imx8m/ddr_init.c | |
| parent | 3f63d27c177a84dd97f77fb843ff4e4c6d7d45eb (diff) | |
| download | u-boot-b335966958a93e49439bf248adadce89e7e2bee3.tar.xz | |
drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue
Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr/imx/imx8m/ddr_init.c')
| -rw-r--r-- | drivers/ddr/imx/imx8m/ddr_init.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index 664966c41b..99a67edfb0 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -190,6 +190,9 @@ int ddr_init(struct dram_timing_info *dram_timing) /* Step15: Set SWCTL.sw_done to 0 */ reg32_write(DDRC_SWCTL(0), 0x00000000); + /* Apply rank-to-rank workaround */ + update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); + /* Step16: Set DFIMISC.dfi_init_start to 1 */ setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); |