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| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-12-30 18:59:24 +0300 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-18 19:49:09 +0300 |
| commit | 4acc71193004d2a7eb21a2672ed1822be9007c77 (patch) | |
| tree | ee9b6597621711f5a8b28d18d96eb6eafca0ee09 /drivers/clk/sunxi/clk_a10s.c | |
| parent | 6239a6d0920a767a32c1384d0aca10648fa37270 (diff) | |
| download | u-boot-4acc71193004d2a7eb21a2672ed1822be9007c77.tar.xz | |
clk: sunxi: Implement UART clocks
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/clk/sunxi/clk_a10s.c')
| -rw-r--r-- | drivers/clk/sunxi/clk_a10s.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index bf91018fc2..aa904ce067 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -17,6 +17,11 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), [CLK_AHB_OHCI] = GATE(0x060, BIT(2)), + [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), + [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), + [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), + [CLK_APB1_UART3] = GATE(0x06c, BIT(19)), + [CLK_USB_OHCI] = GATE(0x0cc, BIT(6)), [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), |