diff options
author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-10 04:14:37 +0300 |
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committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:35 +0300 |
commit | e81a6b4b7a58f56772b48db74ccadfc77a733fe1 (patch) | |
tree | 9bf608e56351ea62afb9e761e4c91acd536890d7 /board | |
parent | 987a20bf9b0d146127559e0414c5d9607d41f601 (diff) | |
download | u-boot-e81a6b4b7a58f56772b48db74ccadfc77a733fe1.tar.xz |
board:starfive: add starfive evb board support
Add board support for StarFive EVB.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/starfive/evb/Kconfig | 52 | ||||
-rw-r--r-- | board/starfive/evb/MAINTAINERS | 7 | ||||
-rw-r--r-- | board/starfive/evb/Makefile | 9 | ||||
-rw-r--r-- | board/starfive/evb/spl.c | 85 | ||||
-rw-r--r-- | board/starfive/evb/starfive_evb.c | 208 |
5 files changed, 361 insertions, 0 deletions
diff --git a/board/starfive/evb/Kconfig b/board/starfive/evb/Kconfig new file mode 100644 index 0000000000..9810944623 --- /dev/null +++ b/board/starfive/evb/Kconfig @@ -0,0 +1,52 @@ +if TARGET_STARFIVE_EVB + +config SYS_CPU + default "jh7110" + +config SYS_BOARD + default "evb" + +config SYS_VENDOR + default "starfive" + +config SYS_CONFIG_NAME + default "starfive-evb" + +config ENV_SIZE + default 0x2000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x140000 if ENV_IS_IN_SPI_FLASH + +config SYS_TEXT_BASE + default 0x40200000 if SPL + default 0x40000000 if !RISCV_SMODE + default 0x40200000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x08000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select STARFIVE_JH7110 + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_GPT + imply PARTITION_TYPE_GUID + imply CMD_NET + imply CMD_PING + imply CMD_SF + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply PHY_LIB + imply PHY_MSCC + +endif diff --git a/board/starfive/evb/MAINTAINERS b/board/starfive/evb/MAINTAINERS new file mode 100644 index 0000000000..82c0454b7c --- /dev/null +++ b/board/starfive/evb/MAINTAINERS @@ -0,0 +1,7 @@ +STARFIVE JH7110 EVB BOARD +M: startfive +S: Maintained +F: arch/riscv/include/asm/arch-jh7110/ +F: board/starfive/evb/ +F: include/configs/starfive-evb.h +F: configs/starfive_evb_defconfig diff --git a/board/starfive/evb/Makefile b/board/starfive/evb/Makefile new file mode 100644 index 0000000000..fc8867306f --- /dev/null +++ b/board/starfive/evb/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd. +# + +obj-y := starfive_evb.o + +obj-$(CONFIG_SPL_BUILD) += spl.o + diff --git a/board/starfive/evb/spl.c b/board/starfive/evb/spl.c new file mode 100644 index 0000000000..44d2a4cc77 --- /dev/null +++ b/board/starfive/evb/spl.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <init.h> +#include <spl.h> +#include <log.h> +#include <linux/delay.h> +#include <image.h> +#include <asm/arch/spl.h> +#include <asm/io.h> + +#define MODE_SELECT_REG 0x1702002c + +int spl_board_init_f(void) +{ + int ret; + + ret = spl_soc_init(); + if (ret) { + debug("JH7110 SPL init failed: %d\n", ret); + return ret; + } + + return 0; +} + +u32 spl_boot_device(void) +{ + int boot_mode = 0; + + boot_mode = readl((const volatile void *)MODE_SELECT_REG) & 0x3; + switch (boot_mode) { + case 0: + return BOOT_DEVICE_SPI; + case 1: + return BOOT_DEVICE_MMC2; + case 2: + return BOOT_DEVICE_MMC1; + case 3: + return BOOT_DEVICE_UART; + default: + debug("Unsupported boot device 0x%x.\n", + boot_mode); + return BOOT_DEVICE_NONE; + } +} + +struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR); +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + arch_cpu_init_dm(); + + preloader_console_init(); + + ret = spl_board_init_f(); + if (ret) { + debug("spl_board_init_f init failed: %d\n", ret); + return; + } +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif + + diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c new file mode 100644 index 0000000000..aa3899c03b --- /dev/null +++ b/board/starfive/evb/starfive_evb.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/jh7110-regs.h> +#include <cpu_func.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <env.h> +#include <inttypes.h> +#include <misc.h> +#include <linux/bitops.h> +#include <asm/arch/gpio.h> + +#define SYS_IOMUX_DOEN(gpio, oen) \ + clrsetbits_le32(SYS_IOMUX_BASE+GPIO_OFFSET(gpio), \ + GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \ + (oen) << GPIO_SHIFT(gpio)) + +#define SYS_IOMUX_DOUT(gpio, gpo) \ + clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DOUT + GPIO_OFFSET(gpio),\ + GPIO_DOUT_MASK << GPIO_SHIFT(gpio),\ + ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio)) + +#define SYS_IOMUX_DIN(gpio, gpi)\ + clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DIN + GPIO_OFFSET(gpi),\ + GPIO_DIN_MASK << GPIO_SHIFT(gpi),\ + ((gpio+2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) + +#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) do {\ + SYS_IOMUX_DOEN(gpio, oen);\ + SYS_IOMUX_DOUT(gpio, gpo);\ + SYS_IOMUX_DIN(gpio, gpi); \ + } while (0) + +#define SYS_CLOCK_ENABLE(clk) \ + setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK) + +static void sys_reset_clear(ulong assert, ulong status, u32 rst) +{ + u32 value; + + clrbits_le32(SYS_CRG_BASE + assert, BIT(rst)); + do { + value = in_le32(SYS_CRG_BASE + status); + } while ((value & BIT(rst)) != BIT(rst)); +} + +static void jh7110_timer_init(void) +{ + SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT); + SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT); + SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT); + SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT); + SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT); + + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT); + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT); + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT); + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT); + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT); +} + +static void jh7110_gmac_init(int id) +{ + switch (id) { + case 0: + clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12, + GMAC5_0_SEL_I_MASK, + BIT(GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK); + break; + + case 1: + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144, + GMAC5_1_SEL_I_MASK, + BIT(GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK); + break; + + default: + break; + } +} + +static void jh7110_usb_init(void) +{ + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_MODE_STRAP_MASK, + (2<<USB_MODE_STRAP_SHIFT) & USB_MODE_STRAP_MASK); + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_OTG_SUSPENDM_BYPS_MASK, + BIT(USB_OTG_SUSPENDM_BYPS_SHIFT) + & USB_OTG_SUSPENDM_BYPS_MASK); + + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_OTG_SUSPENDM_MASK, + BIT(USB_OTG_SUSPENDM_SHIFT) & USB_OTG_SUSPENDM_MASK); + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_PLL_EN_MASK, + BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK); + clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4, + USB_REFCLK_MODE_MASK, + BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK); + + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, + PDRSTN_SPLIT_MASK, + BIT(PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK); + clrsetbits_le32(SYS_IOMUX_BASE + SYS_IOMUX_32, + IOMUX_USB_MASK, + BIT(IOMUX_USB_SHIFT) & IOMUX_USB_MASK); +} + +static void jh7110_mmc_init(int id) +{ + if (id == 0) { + SYS_IOMUX_DOEN(62, LOW); + SYS_IOMUX_DOUT(62, 19); + } else { + SYS_IOMUX_DOEN(10, LOW); + SYS_IOMUX_DOUT(10, 55); + SYS_IOMUX_COMPLEX(9, 44, 57, 19); + SYS_IOMUX_COMPLEX(11, 45, 58, 20); + SYS_IOMUX_COMPLEX(12, 46, 59, 21); + SYS_IOMUX_COMPLEX(7, 47, 60, 22); + SYS_IOMUX_COMPLEX(8, 48, 61, 23); + } +} + +/*enable U74-mc hart1~hart4 prefetcher*/ +static void enable_prefetcher(void) +{ + u32 hart; + u32 *reg; +#define L2_PREFETCHER_BASE_ADDR 0x2030000 +#define L2_PREFETCHER_OFFSET 0x2000 + + /*hart1~hart4*/ + for (hart = 1; hart < 5; hart++) { + reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR + + hart*L2_PREFETCHER_OFFSET)); + + mb(); /* memory barrier */ + setbits_le32(reg, 0x1); + mb(); /* memory barrier */ + } +} + +int board_init(void) +{ + enable_caches(); + + /*enable hart1-hart4 prefetcher*/ +// enable_prefetcher(); + + jh7110_gmac_init(0); + jh7110_gmac_init(1); + jh7110_timer_init(); + + jh7110_usb_init(); + + jh7110_mmc_init(0); + jh7110_mmc_init(1); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R + +int misc_init_r(void) +{ + char mac[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad }; + +#if CONFIG_IS_ENABLED(STARFIVE_OTP) + struct udevice *dev; + char buf[8]; + int ret; +#define MACADDR_OFFSET 0x8 + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(starfive_otp), &dev); + if (ret) { + debug("%s: could not find otp device\n", __func__); + goto err; + } + + ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf)); + if (ret) + printf("%s: error reading mac from OTP\n", __func__); + else + if (buf[0] != 0xff) + memcpy(mac, buf, 6); +err: +#endif + eth_env_set_enetaddr("ethaddr", mac); + + return 0; +} +#endif + |