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authorMinda Chen <minda.chen@starfivetech.com>2024-05-17 06:19:06 +0300
committerMinda Chen <minda.chen@starfivetech.com>2024-05-21 04:41:21 +0300
commit2ea92a2ccc63283f0e6bb23e8f58a4e43547dd83 (patch)
tree12b60a06789251478c45afde74da7ef6bf281b8f /board
parentfc399f0cfa0b31325b3a750a206656804b963e29 (diff)
downloadu-boot-2ea92a2ccc63283f0e6bb23e8f58a4e43547dd83.tar.xz
spl: amp: Enable devkits UART2 and move rtos image to memory
Enable devkits UART2 for rtos and move rtos image to running memory. The image size is 832KB. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Diffstat (limited to 'board')
-rw-r--r--board/starfive/devkits/spl.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/board/starfive/devkits/spl.c b/board/starfive/devkits/spl.c
index d5f43b4747..d20c74b3a5 100644
--- a/board/starfive/devkits/spl.c
+++ b/board/starfive/devkits/spl.c
@@ -18,6 +18,8 @@
#define MODE_SELECT_REG 0x1702002c
+DECLARE_GLOBAL_DATA_PTR;
+
int spl_board_init_f(void)
{
int ret;
@@ -163,4 +165,37 @@ int board_fit_config_name_match(const char *name)
}
#endif
+static void spl_enable_uart2(void)
+{
+ /* uart2 clock */
+ setbits_le32(SYS_CRG_BASE + CLK_UART2_APB_OFFSET, BIT(31));
+ setbits_le32(SYS_CRG_BASE + CLK_UART2_CORE_OFFSET, BIT(31));
+ clrsetbits_le32(SYS_CRG_BASE + CLK_RSTN_3_OFFSET, BIT(23) | BIT(24), 0);
+
+ /*uart2 tx*/
+ SYS_IOMUX_DOEN(45, LOW);
+ SYS_IOMUX_DOUT(45, 0x4f);
+ SYS_IOMUX_SET_DS(45, 3);
+ /*uart2 rx*/
+ SYS_IOMUX_DOEN(46, HIGH);
+ SYS_IOMUX_DOUT(46, 0);
+ SYS_IOMUX_DIN(46, 62);
+}
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ unsigned long rtos_offset, rtos_image_addr;
+ unsigned long rtos_base;
+
+ rtos_base = fdtdec_get_config_int(gd->fdt_blob,
+ "amp,rtos-code-base", 0);
+ rtos_offset = fdtdec_get_config_int(gd->fdt_blob,
+ "amp,rtos-offset", 0);
+
+ if (rtos_base && rtos_offset) {
+ spl_enable_uart2();
+ rtos_image_addr = CONFIG_SPL_OPENSBI_LOAD_ADDR + rtos_offset;
+ memcpy((void *)rtos_base, (void *)(rtos_image_addr),
+ spl_image->size - rtos_offset);
+ }
+}