diff options
author | andy.hu <andy.hu@starfivetech.com> | 2024-05-31 11:25:42 +0300 |
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committer | andy.hu <andy.hu@starfivetech.com> | 2024-05-31 11:25:42 +0300 |
commit | 2519a0e18a42d88b399934af6870fc2bc0fbc348 (patch) | |
tree | 12b60a06789251478c45afde74da7ef6bf281b8f | |
parent | 7572e010f531c4aea2c8d6fd9ad0bd626028b464 (diff) | |
parent | 2ea92a2ccc63283f0e6bb23e8f58a4e43547dd83 (diff) | |
download | u-boot-2519a0e18a42d88b399934af6870fc2bc0fbc348.tar.xz |
Merge branch 'CR_11009_devkits_uboot_amp_minda' into 'jh7110-master'
CR_11009 amp: Set devkits mac addr to share ram while one gmac is disable.
See merge request sdk/u-boot!84
-rw-r--r-- | board/starfive/devkits/spl.c | 35 | ||||
-rw-r--r-- | board/starfive/devkits/starfive_devkits.c | 22 |
2 files changed, 55 insertions, 2 deletions
diff --git a/board/starfive/devkits/spl.c b/board/starfive/devkits/spl.c index d5f43b4747..d20c74b3a5 100644 --- a/board/starfive/devkits/spl.c +++ b/board/starfive/devkits/spl.c @@ -18,6 +18,8 @@ #define MODE_SELECT_REG 0x1702002c +DECLARE_GLOBAL_DATA_PTR; + int spl_board_init_f(void) { int ret; @@ -163,4 +165,37 @@ int board_fit_config_name_match(const char *name) } #endif +static void spl_enable_uart2(void) +{ + /* uart2 clock */ + setbits_le32(SYS_CRG_BASE + CLK_UART2_APB_OFFSET, BIT(31)); + setbits_le32(SYS_CRG_BASE + CLK_UART2_CORE_OFFSET, BIT(31)); + clrsetbits_le32(SYS_CRG_BASE + CLK_RSTN_3_OFFSET, BIT(23) | BIT(24), 0); + + /*uart2 tx*/ + SYS_IOMUX_DOEN(45, LOW); + SYS_IOMUX_DOUT(45, 0x4f); + SYS_IOMUX_SET_DS(45, 3); + /*uart2 rx*/ + SYS_IOMUX_DOEN(46, HIGH); + SYS_IOMUX_DOUT(46, 0); + SYS_IOMUX_DIN(46, 62); +} +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + unsigned long rtos_offset, rtos_image_addr; + unsigned long rtos_base; + + rtos_base = fdtdec_get_config_int(gd->fdt_blob, + "amp,rtos-code-base", 0); + rtos_offset = fdtdec_get_config_int(gd->fdt_blob, + "amp,rtos-offset", 0); + + if (rtos_base && rtos_offset) { + spl_enable_uart2(); + rtos_image_addr = CONFIG_SPL_OPENSBI_LOAD_ADDR + rtos_offset; + memcpy((void *)rtos_base, (void *)(rtos_image_addr), + spl_image->size - rtos_offset); + } +} diff --git a/board/starfive/devkits/starfive_devkits.c b/board/starfive/devkits/starfive_devkits.c index 66c1918e31..8fd1cb4784 100644 --- a/board/starfive/devkits/starfive_devkits.c +++ b/board/starfive/devkits/starfive_devkits.c @@ -28,6 +28,8 @@ #define SYS_CLOCK_ENABLE(clk) \ setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK) +DECLARE_GLOBAL_DATA_PTR; + #define CPU_VOL_BINNING_OFFSET 0x7fc enum { BOOT_FLASH = 0, @@ -372,7 +374,9 @@ err: int board_late_init(void) { struct udevice *dev; - int ret; + int ret, offset; + u8 mac0[6], mac1[6]; + u64 share_ram_addr; get_boot_mode(); @@ -394,8 +398,22 @@ int board_late_init(void) if (ret) goto err; + /* AMP case : write MAC to share ram */ + offset = fdt_path_offset(gd->fdt_blob, + "/chosen/opensbi-domains/rpmsg_shmem"); + if (offset >= 0) { + share_ram_addr = + fdtdec_get_uint64(gd->fdt_blob, offset, "base", 0); + if (share_ram_addr) { + eth_env_get_enetaddr("eth0addr", mac0); + eth_env_get_enetaddr("eth1addr", mac1); + memcpy((void *)share_ram_addr, mac0, 6); + memcpy((void *)(share_ram_addr + 8), mac1, 6); + } + } + err: - return 0; + return 0; } |