diff options
| author | leyfoon.tan <leyfoon.tan@starfivetech.com> | 2024-09-07 09:27:08 +0300 |
|---|---|---|
| committer | leyfoon.tan <leyfoon.tan@starfivetech.com> | 2024-09-07 09:27:08 +0300 |
| commit | d9b70aaf1a76ce48374e83c323bdd4ed98871f56 (patch) | |
| tree | 2fc9c14fb8e1564f457ad328f18d6a10d72de58e | |
| parent | 89b6b13a57b2fa437ca21fe27148eb80fee4ea19 (diff) | |
| parent | 7077cfc5285121e7902301bb4dd2d0b8f6483392 (diff) | |
| download | u-boot-dubhe_fpga_dev_v2023.10.tar.xz | |
Merge branch 'dubhe_fpga_dev_v2023.10_sync_linux_v6.6.48_dts' into 'dubhe_fpga_dev_v2023.10'REL_DUBHE_SEPT2024dubhe_fpga_dev_v2023.10
riscv: dts: dubhe: Sync device tree from Linux
See merge request starfive-tech/u-boot!162
| -rw-r--r-- | arch/riscv/dts/dubhe.dtsi | 12 | ||||
| -rw-r--r-- | arch/riscv/dts/dubhe70-cpus.dtsi | 16 | ||||
| -rw-r--r-- | arch/riscv/dts/dubhe70_fpga.dts | 5 | ||||
| -rw-r--r-- | arch/riscv/dts/dubhe80-cpus.dtsi | 1 |
4 files changed, 24 insertions, 10 deletions
diff --git a/arch/riscv/dts/dubhe.dtsi b/arch/riscv/dts/dubhe.dtsi index 168ca7bd31..3d43717fa7 100644 --- a/arch/riscv/dts/dubhe.dtsi +++ b/arch/riscv/dts/dubhe.dtsi @@ -153,8 +153,16 @@ snps,axi-config = <&stmmac_axi_setup>; snps,tso; snps,en-tx-lpi-clockgating; - snps,txpbl = <4>; - snps,rxpbl = <4>; + snps,txpbl = <2>; + snps,rxpbl = <2>; + status = "disabled"; + }; + + l3_pmu: pmu@12900000 { + compatible = "starfive,jh8100-starlink-pmu"; + reg = <0x0 0x12900000 0x0 0x10000>; + interrupt-parent = <&plic0>; + interrupts = <3>; status = "disabled"; }; }; diff --git a/arch/riscv/dts/dubhe70-cpus.dtsi b/arch/riscv/dts/dubhe70-cpus.dtsi index a5b12ad4ef..9714d014b5 100644 --- a/arch/riscv/dts/dubhe70-cpus.dtsi +++ b/arch/riscv/dts/dubhe70-cpus.dtsi @@ -43,12 +43,12 @@ d-cache-sets = <512>; d-cache-size = <32768>; d-tlb-sets = <1>; - d-tlb-size = <16>; + d-tlb-size = <24>; i-cache-block-size = <64>; i-cache-sets = <512>; i-cache-size = <32768>; i-tlb-sets = <1>; - i-tlb-size = <24>; + i-tlb-size = <16>; next-level-cache = <&l2_cache0>; tlb-split; @@ -76,12 +76,12 @@ d-cache-sets = <512>; d-cache-size = <32768>; d-tlb-sets = <1>; - d-tlb-size = <16>; + d-tlb-size = <24>; i-cache-block-size = <64>; i-cache-sets = <512>; i-cache-size = <32768>; i-tlb-sets = <1>; - i-tlb-size = <24>; + i-tlb-size = <16>; next-level-cache = <&l2_cache1>; tlb-split; @@ -109,12 +109,12 @@ d-cache-sets = <512>; d-cache-size = <32768>; d-tlb-sets = <1>; - d-tlb-size = <16>; + d-tlb-size = <24>; i-cache-block-size = <64>; i-cache-sets = <512>; i-cache-size = <32768>; i-tlb-sets = <1>; - i-tlb-size = <24>; + i-tlb-size = <16>; next-level-cache = <&l2_cache2>; tlb-split; @@ -142,12 +142,12 @@ d-cache-sets = <512>; d-cache-size = <32768>; d-tlb-sets = <1>; - d-tlb-size = <16>; + d-tlb-size = <24>; i-cache-block-size = <64>; i-cache-sets = <512>; i-cache-size = <32768>; i-tlb-sets = <1>; - i-tlb-size = <24>; + i-tlb-size = <16>; next-level-cache = <&l2_cache3>; tlb-split; diff --git a/arch/riscv/dts/dubhe70_fpga.dts b/arch/riscv/dts/dubhe70_fpga.dts index 15cc7f3715..cb42c3886c 100644 --- a/arch/riscv/dts/dubhe70_fpga.dts +++ b/arch/riscv/dts/dubhe70_fpga.dts @@ -10,3 +10,8 @@ dma-coherent; }; }; + +&l3_pmu { + compatible = "starfive,dubhe70-starlink-pmu", "starfive,jh8100-starlink-pmu"; + status = "okay"; +}; diff --git a/arch/riscv/dts/dubhe80-cpus.dtsi b/arch/riscv/dts/dubhe80-cpus.dtsi index 5861b48844..6d6a88dc5c 100644 --- a/arch/riscv/dts/dubhe80-cpus.dtsi +++ b/arch/riscv/dts/dubhe80-cpus.dtsi @@ -159,6 +159,7 @@ }; l2_cache0: cache-controller-0 { + compatible = "cache"; cache-block-size = <64>; cache-level = <2>; cache-sets = <1024>; |