1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
|
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2019 FORTH-ICS/CARV
* Panagiotis Peristerakis <perister@ics.forth.gr>
*/
#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_const.h>
#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/ipi/aclint_mswi.h>
#include <sbi_utils/irqchip/plic.h>
#include <sbi_utils/serial/uart8250.h>
#include <sbi_utils/timer/aclint_mtimer.h>
#define ARIANE_UART_ADDR 0x10000000
#define ARIANE_UART_FREQ 50000000
#define ARIANE_UART_BAUDRATE 115200
#define ARIANE_UART_REG_SHIFT 2
#define ARIANE_UART_REG_WIDTH 4
#define ARIANE_UART_REG_OFFSET 0
#define ARIANE_PLIC_ADDR 0xc000000
#define ARIANE_PLIC_SIZE (0x200000 + \
(ARIANE_HART_COUNT * 0x1000))
#define ARIANE_PLIC_NUM_SOURCES 3
#define ARIANE_HART_COUNT 1
#define ARIANE_CLINT_ADDR 0x2000000
#define ARIANE_ACLINT_MTIMER_FREQ 1000000
#define ARIANE_ACLINT_MSWI_ADDR (ARIANE_CLINT_ADDR + \
CLINT_MSWI_OFFSET)
#define ARIANE_ACLINT_MTIMER_ADDR (ARIANE_CLINT_ADDR + \
CLINT_MTIMER_OFFSET)
static struct plic_data plic = {
.addr = ARIANE_PLIC_ADDR,
.size = ARIANE_PLIC_SIZE,
.num_src = ARIANE_PLIC_NUM_SOURCES,
.flags = PLIC_FLAG_ARIANE_BUG,
.context_map = {
[0] = { 0, 1 },
},
};
static struct aclint_mswi_data mswi = {
.addr = ARIANE_ACLINT_MSWI_ADDR,
.size = ACLINT_MSWI_SIZE,
.first_hartid = 0,
.hart_count = ARIANE_HART_COUNT,
};
static struct aclint_mtimer_data mtimer = {
.mtime_freq = ARIANE_ACLINT_MTIMER_FREQ,
.mtime_addr = ARIANE_ACLINT_MTIMER_ADDR +
ACLINT_DEFAULT_MTIME_OFFSET,
.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
.mtimecmp_addr = ARIANE_ACLINT_MTIMER_ADDR +
ACLINT_DEFAULT_MTIMECMP_OFFSET,
.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
.first_hartid = 0,
.hart_count = ARIANE_HART_COUNT,
.has_64bit_mmio = true,
};
/*
* Ariane platform early initialization.
*/
static int ariane_early_init(bool cold_boot)
{
if (!cold_boot)
return 0;
return uart8250_init(ARIANE_UART_ADDR,
ARIANE_UART_FREQ,
ARIANE_UART_BAUDRATE,
ARIANE_UART_REG_SHIFT,
ARIANE_UART_REG_WIDTH,
ARIANE_UART_REG_OFFSET);
}
/*
* Ariane platform final initialization.
*/
static int ariane_final_init(bool cold_boot)
{
void *fdt;
if (!cold_boot)
return 0;
fdt = fdt_get_address_rw();
fdt_fixups(fdt);
return 0;
}
/*
* Initialize the ariane interrupt controller during cold boot.
*/
static int ariane_irqchip_init(void)
{
return plic_cold_irqchip_init(&plic);
}
/*
* Initialize IPI during cold boot.
*/
static int ariane_ipi_init(void)
{
return aclint_mswi_cold_init(&mswi);
}
/*
* Initialize ariane timer during cold boot.
*/
static int ariane_timer_init(void)
{
return aclint_mtimer_cold_init(&mtimer, NULL);
}
/*
* Platform descriptor.
*/
const struct sbi_platform_operations platform_ops = {
.early_init = ariane_early_init,
.final_init = ariane_final_init,
.irqchip_init = ariane_irqchip_init,
.ipi_init = ariane_ipi_init,
.timer_init = ariane_timer_init,
};
const struct sbi_platform platform = {
.opensbi_version = OPENSBI_VERSION,
.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
.name = "ARIANE RISC-V",
.features = SBI_PLATFORM_DEFAULT_FEATURES,
.hart_count = ARIANE_HART_COUNT,
.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
.heap_size = SBI_PLATFORM_DEFAULT_HEAP_SIZE(ARIANE_HART_COUNT),
.platform_ops_addr = (unsigned long)&platform_ops
};
|
