1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
[
{
"BriefDescription": "Memory accesses that missed the DTLB.",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS",
"SampleAfterValue": "200000",
"UMask": "0x7"
},
{
"BriefDescription": "DTLB misses due to load operations.",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
"SampleAfterValue": "200000",
"UMask": "0x5"
},
{
"BriefDescription": "DTLB misses due to store operations.",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
"SampleAfterValue": "200000",
"UMask": "0x6"
},
{
"BriefDescription": "L0 DTLB misses due to load operations.",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
"SampleAfterValue": "200000",
"UMask": "0x9"
},
{
"BriefDescription": "L0 DTLB misses due to store operations",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
"SampleAfterValue": "200000",
"UMask": "0xa"
},
{
"BriefDescription": "ITLB flushes.",
"Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.FLUSH",
"SampleAfterValue": "200000",
"UMask": "0x4"
},
{
"BriefDescription": "ITLB hits.",
"Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.HIT",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "ITLB misses.",
"Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.MISSES",
"PEBS": "2",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "Retired loads that miss the DTLB (precise event).",
"Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
"SampleAfterValue": "200000",
"UMask": "0x4"
},
{
"BriefDescription": "Duration of page-walks in core cycles",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "2000000",
"UMask": "0x3"
},
{
"BriefDescription": "Duration of D-side only page walks",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Number of D-side only page walks",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "Duration of I-Side page walks",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "Number of I-Side page walks",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page-walks executed.",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "200000",
"UMask": "0x3"
}
]
|
