1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
|
/*
* Copyright (C) 2011 Marvell International Ltd. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/usb/otg.h>
#include <linux/platform_data/mv_usb.h>
#include "phy-mv-u3d-usb.h"
/*
* struct mv_u3d_phy - transceiver driver state
* @phy: transceiver structure
* @dev: The parent device supplied to the probe function
* @clk: usb phy clock
* @base: usb phy register memory base
*/
struct mv_u3d_phy {
struct usb_phy phy;
struct mv_usb_platform_data *plat;
struct device *dev;
struct clk *clk;
void __iomem *base;
};
static u32 mv_u3d_phy_read(void __iomem *base, u32 reg)
{
void __iomem *addr, *data;
addr = base;
data = base + 0x4;
writel_relaxed(reg, addr);
return readl_relaxed(data);
}
static void mv_u3d_phy_set(void __iomem *base, u32 reg, u32 value)
{
void __iomem *addr, *data;
u32 tmp;
addr = base;
data = base + 0x4;
writel_relaxed(reg, addr);
tmp = readl_relaxed(data);
tmp |= value;
writel_relaxed(tmp, data);
}
static void mv_u3d_phy_clear(void __iomem *base, u32 reg, u32 value)
{
void __iomem *addr, *data;
u32 tmp;
addr = base;
data = base + 0x4;
writel_relaxed(reg, addr);
tmp = readl_relaxed(data);
tmp &= ~value;
writel_relaxed(tmp, data);
}
static void mv_u3d_phy_write(void __iomem *base, u32 reg, u32 value)
{
void __iomem *addr, *data;
addr = base;
data = base + 0x4;
writel_relaxed(reg, addr);
writel_relaxed(value, data);
}
void mv_u3d_phy_shutdown(struct usb_phy *phy)
{
struct mv_u3d_phy *mv_u3d_phy;
void __iomem *base;
u32 val;
mv_u3d_phy = container_of(phy, struct mv_u3d_phy, phy);
base = mv_u3d_phy->base;
/* Power down Reference Analog current, bit 15
* Power down PLL, bit 14
* Power down Receiver, bit 13
* Power down Transmitter, bit 12
* of USB3_POWER_PLL_CONTROL register
*/
val = mv_u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
val &= ~(USB3_POWER_PLL_CONTROL_PU);
mv_u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
if (mv_u3d_phy->clk)
clk_disable(mv_u3d_phy->clk);
}
static int mv_u3d_phy_init(struct usb_phy *phy)
{
struct mv_u3d_phy *mv_u3d_phy;
void __iomem *base;
u32 val, count;
/* enable usb3 phy */
mv_u3d_phy = container_of(phy, struct mv_u3d_phy, phy);
if (mv_u3d_phy->clk)
clk_enable(mv_u3d_phy->clk);
base = mv_u3d_phy->base;
val = mv_u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
val &= ~(USB3_POWER_PLL_CONTROL_PU_MASK);
val |= 0xF << USB3_POWER_PLL_CONTROL_PU_SHIFT;
mv_u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
udelay(100);
mv_u3d_phy_write(base, USB3_RESET_CONTROL,
USB3_RESET_CONTROL_RESET_PIPE);
udelay(100);
mv_u3d_phy_write(base, USB3_RESET_CONTROL,
USB3_RESET_CONTROL_RESET_PIPE
| USB3_RESET_CONTROL_RESET_PHY);
udelay(100);
val = mv_u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
val &= ~(USB3_POWER_PLL_CONTROL_REF_FREF_SEL_MASK
| USB3_POWER_PLL_CONTROL_PHY_MODE_MASK);
val |= (USB3_PLL_25MHZ << USB3_POWER_PLL_CONTROL_REF_FREF_SEL_SHIFT)
| (0x5 << USB3_POWER_PLL_CONTROL_PHY_MODE_SHIFT);
mv_u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
udelay(100);
mv_u3d_phy_clear(base, USB3_KVCO_CALI_CONTROL,
USB3_KVCO_CALI_CONTROL_USE_MAX_PLL_RATE_MASK);
udelay(100);
val = mv_u3d_phy_read(base, USB3_SQUELCH_FFE);
val &= ~(USB3_SQUELCH_FFE_FFE_CAP_SEL_MASK
| USB3_SQUELCH_FFE_FFE_RES_SEL_MASK
| USB3_SQUELCH_FFE_SQ_THRESH_IN_MASK);
val |= ((0xD << USB3_SQUELCH_FFE_FFE_CAP_SEL_SHIFT)
| (0x7 << USB3_SQUELCH_FFE_FFE_RES_SEL_SHIFT)
| (0x8 << USB3_SQUELCH_FFE_SQ_THRESH_IN_SHIFT));
mv_u3d_phy_write(base, USB3_SQUELCH_FFE, val);
udelay(100);
val = mv_u3d_phy_read(base, USB3_GEN1_SET0);
val &= ~USB3_GEN1_SET0_G1_TX_SLEW_CTRL_EN_MASK;
val |= 1 << USB3_GEN1_SET0_G1_TX_EMPH_EN_SHIFT;
mv_u3d_phy_write(base, USB3_GEN1_SET0, val);
udelay(100);
val = mv_u3d_phy_read(base, USB3_GEN2_SET0);
val &= ~(USB3_GEN2_SET0_G2_TX_AMP_MASK
| USB3_GEN2_SET0_G2_TX_EMPH_AMP_MASK
| USB3_GEN2_SET0_G2_TX_SLEW_CTRL_EN_MASK);
val |= ((0x14 << USB3_GEN2_SET0_G2_TX_AMP_SHIFT)
| (1 << USB3_GEN2_SET0_G2_TX_AMP_ADJ_SHIFT)
| (0xA << USB3_GEN2_SET0_G2_TX_EMPH_AMP_SHIFT)
| (1 << USB3_GEN2_SET0_G2_TX_EMPH_EN_SHIFT));
mv_u3d_phy_write(base, USB3_GEN2_SET0, val);
udelay(100);
mv_u3d_phy_read(base, USB3_TX_EMPPH);
val &= ~(USB3_TX_EMPPH_AMP_MASK
| USB3_TX_EMPPH_EN_MASK
| USB3_TX_EMPPH_AMP_FORCE_MASK
| USB3_TX_EMPPH_PAR1_MASK
| USB3_TX_EMPPH_PAR2_MASK);
val |= ((0xB << USB3_TX_EMPPH_AMP_SHIFT)
| (1 << USB3_TX_EMPPH_EN_SHIFT)
| (1 << USB3_TX_EMPPH_AMP_FORCE_SHIFT)
| (0x1C << USB3_TX_EMPPH_PAR1_SHIFT)
| (1 << USB3_TX_EMPPH_PAR2_SHIFT));
mv_u3d_phy_write(base, USB3_TX_EMPPH, val);
udelay(100);
val = mv_u3d_phy_read(base, USB3_GEN2_SET1);
val &= ~(USB3_GEN2_SET1_G2_RX_SELMUPI_MASK
| USB3_GEN2_SET1_G2_RX_SELMUPF_MASK
| USB3_GEN2_SET1_G2_RX_SELMUFI_MASK
| USB3_GEN2_SET1_G2_RX_SELMUFF_MASK);
val |= ((1 << USB3_GEN2_SET1_G2_RX_SELMUPI_SHIFT)
| (1 << USB3_GEN2_SET1_G2_RX_SELMUPF_SHIFT)
| (1 << USB3_GEN2_SET1_G2_RX_SELMUFI_SHIFT)
| (1 << USB3_GEN2_SET1_G2_RX_SELMUFF_SHIFT));
mv_u3d_phy_write(base, USB3_GEN2_SET1, val);
udelay(100);
val = mv_u3d_phy_read(base, USB3_DIGITAL_LOOPBACK_EN);
val &= ~USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_MASK;
val |= 1 << USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_SHIFT;
mv_u3d_phy_write(base, USB3_DIGITAL_LOOPBACK_EN, val);
udelay(100);
val = mv_u3d_phy_read(base, USB3_IMPEDANCE_TX_SSC);
val &= ~USB3_IMPEDANCE_TX_SSC_SSC_AMP_MASK;
val |= 0xC << USB3_IMPEDANCE_TX_SSC_SSC_AMP_SHIFT;
mv_u3d_phy_write(base, USB3_IMPEDANCE_TX_SSC, val);
udelay(100);
val = mv_u3d_phy_read(base, USB3_IMPEDANCE_CALI_CTRL);
val &= ~USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_MASK;
val |= 0x4 << USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_SHIFT;
mv_u3d_phy_write(base, USB3_IMPEDANCE_CALI_CTRL, val);
udelay(100);
val = mv_u3d_phy_read(base, USB3_PHY_ISOLATION_MODE);
val &= ~(USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_MASK
| USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_MASK
| USB3_PHY_ISOLATION_MODE_TX_DRV_IDLE_MASK);
val |= ((1 << USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_SHIFT)
| (1 << USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_SHIFT));
mv_u3d_phy_write(base, USB3_PHY_ISOLATION_MODE, val);
udelay(100);
val = mv_u3d_phy_read(base, USB3_TXDETRX);
val &= ~(USB3_TXDETRX_VTHSEL_MASK);
val |= 0x1 << USB3_TXDETRX_VTHSEL_SHIFT;
mv_u3d_phy_write(base, USB3_TXDETRX, val);
udelay(100);
dev_dbg(mv_u3d_phy->dev, "start calibration\n");
calstart:
/* Perform Manual Calibration */
mv_u3d_phy_set(base, USB3_KVCO_CALI_CONTROL,
1 << USB3_KVCO_CALI_CONTROL_CAL_START_SHIFT);
mdelay(1);
count = 0;
while (1) {
val = mv_u3d_phy_read(base, USB3_KVCO_CALI_CONTROL);
if (val & (1 << USB3_KVCO_CALI_CONTROL_CAL_DONE_SHIFT))
break;
else if (count > 50) {
dev_dbg(mv_u3d_phy->dev, "calibration failure, retry...\n");
goto calstart;
}
count++;
mdelay(1);
}
/* active PIPE interface */
mv_u3d_phy_write(base, USB3_PIPE_SM_CTRL,
1 << USB3_PIPE_SM_CTRL_PHY_INIT_DONE);
return 0;
}
static int mv_u3d_phy_probe(struct platform_device *pdev)
{
struct mv_u3d_phy *mv_u3d_phy;
struct mv_usb_platform_data *pdata;
struct device *dev = &pdev->dev;
struct resource *res;
void __iomem *phy_base;
int ret;
pdata = pdev->dev.platform_data;
if (!pdata) {
dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
return -EINVAL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "missing mem resource\n");
return -ENODEV;
}
phy_base = devm_ioremap_resource(dev, res);
if (IS_ERR(phy_base))
return PTR_ERR(phy_base);
mv_u3d_phy = devm_kzalloc(dev, sizeof(*mv_u3d_phy), GFP_KERNEL);
if (!mv_u3d_phy)
return -ENOMEM;
mv_u3d_phy->dev = &pdev->dev;
mv_u3d_phy->plat = pdata;
mv_u3d_phy->base = phy_base;
mv_u3d_phy->phy.dev = mv_u3d_phy->dev;
mv_u3d_phy->phy.label = "mv-u3d-phy";
mv_u3d_phy->phy.init = mv_u3d_phy_init;
mv_u3d_phy->phy.shutdown = mv_u3d_phy_shutdown;
ret = usb_add_phy(&mv_u3d_phy->phy, USB_PHY_TYPE_USB3);
if (ret)
goto err;
if (!mv_u3d_phy->clk)
mv_u3d_phy->clk = clk_get(mv_u3d_phy->dev, "u3dphy");
platform_set_drvdata(pdev, mv_u3d_phy);
dev_info(&pdev->dev, "Initialized Marvell USB 3.0 PHY\n");
err:
return ret;
}
static int mv_u3d_phy_remove(struct platform_device *pdev)
{
struct mv_u3d_phy *mv_u3d_phy = platform_get_drvdata(pdev);
usb_remove_phy(&mv_u3d_phy->phy);
if (mv_u3d_phy->clk) {
clk_put(mv_u3d_phy->clk);
mv_u3d_phy->clk = NULL;
}
return 0;
}
static struct platform_driver mv_u3d_phy_driver = {
.probe = mv_u3d_phy_probe,
.remove = mv_u3d_phy_remove,
.driver = {
.name = "mv-u3d-phy",
.owner = THIS_MODULE,
},
};
module_platform_driver(mv_u3d_phy_driver);
MODULE_DESCRIPTION("Marvell USB 3.0 PHY controller");
MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mv-u3d-phy");
|