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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
#define QSERDES_V6_N4_TX_CLKBUF_ENABLE 0x08
#define QSERDES_V6_N4_TX_TX_EMP_POST1_LVL 0x0c
#define QSERDES_V6_N4_TX_TX_DRV_LVL 0x14
#define QSERDES_V6_N4_TX_RESET_TSYNC_EN 0x1c
#define QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN 0x20
#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX 0x30
#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX 0x34
#define QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN 0x48
#define QSERDES_V6_N4_TX_HIGHZ_DRVR_EN 0x4c
#define QSERDES_V6_N4_TX_TX_POL_INV 0x50
#define QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN 0x54
#define QSERDES_V6_N4_TX_LANE_MODE_1 0x78
#define QSERDES_V6_N4_TX_LANE_MODE_2 0x7c
#define QSERDES_V6_N4_TX_LANE_MODE_3 0x80
#define QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN 0xac
#define QSERDES_V6_N4_TX_TX_BAND 0xd8
#define QSERDES_V6_N4_TX_INTERFACE_SELECT 0xe4
#define QSERDES_V6_N4_TX_VMODE_CTRL1 0xb0
#define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2 0x8
#define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2 0x18
#define QSERDES_V6_N4_RX_UCDR_PI_CONTROLS 0x20
#define QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE 0x94
#define QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2 0x9c
#define QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET 0xa0
#define QSERDES_V6_N4_RX_DFE_3 0xb4
#define QSERDES_V6_N4_RX_VGA_CAL_CNTRL1 0xe0
#define QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL 0xe8
#define QSERDES_V6_N4_RX_GM_CAL 0x10c
#define QSERDES_V6_N4_RX_SIGDET_ENABLES 0x148
#define QSERDES_V6_N4_RX_SIGDET_CNTRL 0x14c
#define QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL 0x154
#define QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET 0x194
#define QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc
#define QSERDES_V6_N4_RX_UCDR_PI_CTRL1 0x23c
#define QSERDES_V6_N4_RX_UCDR_PI_CTRL2 0x240
#define QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2 0x27c
#define QSERDES_V6_N4_RX_DFE_DAC_ENABLE1 0x298
#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B0 0x2b8
#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B1 0x2bc
#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B2 0x2c0
#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B3 0x2c4
#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B4 0x2c8
#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B5 0x2cc
#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B6 0x2d0
#define QSERDES_V6_N4_RX_MODE_RATE2_B0 0x2d4
#define QSERDES_V6_N4_RX_MODE_RATE2_B1 0x2d8
#define QSERDES_V6_N4_RX_MODE_RATE2_B2 0x2dc
#define QSERDES_V6_N4_RX_MODE_RATE2_B3 0x2e0
#define QSERDES_V6_N4_RX_MODE_RATE2_B4 0x2e4
#define QSERDES_V6_N4_RX_MODE_RATE2_B5 0x2e8
#define QSERDES_V6_N4_RX_MODE_RATE2_B6 0x2ec
#define QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE 0x30c
#define QSERDES_V6_N4_RX_RX_BKUP_CTRL1 0x310
#endif
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