1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
|
// SPDX-License-Identifier: MIT
/*
* Copyright © 2021 Intel Corporation
*/
#include "intel_guc_rc.h"
#include "gt/intel_gt.h"
#include "i915_drv.h"
static bool __guc_rc_supported(struct intel_guc *guc)
{
/* GuC RC is unavailable for pre-Gen12 */
return guc->submission_supported &&
GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
}
static bool __guc_rc_selected(struct intel_guc *guc)
{
if (!intel_guc_rc_is_supported(guc))
return false;
return guc->submission_selected;
}
void intel_guc_rc_init_early(struct intel_guc *guc)
{
guc->rc_supported = __guc_rc_supported(guc);
guc->rc_selected = __guc_rc_selected(guc);
}
static int guc_action_control_gucrc(struct intel_guc *guc, bool enable)
{
u32 rc_mode = enable ? INTEL_GUCRC_FIRMWARE_CONTROL :
INTEL_GUCRC_HOST_CONTROL;
u32 action[] = {
INTEL_GUC_ACTION_SETUP_PC_GUCRC,
rc_mode
};
int ret;
ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
ret = ret > 0 ? -EPROTO : ret;
return ret;
}
static int __guc_rc_control(struct intel_guc *guc, bool enable)
{
struct intel_gt *gt = guc_to_gt(guc);
struct drm_device *drm = &guc_to_gt(guc)->i915->drm;
int ret;
if (!intel_uc_uses_guc_rc(>->uc))
return -EOPNOTSUPP;
if (!intel_guc_is_ready(guc))
return -EINVAL;
ret = guc_action_control_gucrc(guc, enable);
if (ret) {
drm_err(drm, "Failed to %s GuC RC (%pe)\n",
enabledisable(enable), ERR_PTR(ret));
return ret;
}
drm_info(>->i915->drm, "GuC RC: %s\n",
enableddisabled(enable));
return 0;
}
int intel_guc_rc_enable(struct intel_guc *guc)
{
return __guc_rc_control(guc, true);
}
int intel_guc_rc_disable(struct intel_guc *guc)
{
return __guc_rc_control(guc, false);
}
|
