blob: b47ef5fe703940884564d6b270be9030824ff87b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TXx9 SoC DMA Controller
*/
#ifndef __ASM_TXX9_DMAC_H
#define __ASM_TXX9_DMAC_H
#include <linux/dmaengine.h>
#define TXX9_DMA_MAX_NR_CHANNELS 4
/**
* struct txx9dmac_platform_data - Controller configuration parameters
* @memcpy_chan: Channel used for DMA_MEMCPY
* @have_64bit_regs: DMAC have 64 bit registers
*/
struct txx9dmac_platform_data {
int memcpy_chan;
bool have_64bit_regs;
};
/**
* struct txx9dmac_chan_platform_data - Channel configuration parameters
* @dmac_dev: A platform device for DMAC
*/
struct txx9dmac_chan_platform_data {
struct platform_device *dmac_dev;
};
/**
* struct txx9dmac_slave - Controller-specific information about a slave
* @tx_reg: physical address of data register used for
* memory-to-peripheral transfers
* @rx_reg: physical address of data register used for
* peripheral-to-memory transfers
* @reg_width: peripheral register width
*/
struct txx9dmac_slave {
u64 tx_reg;
u64 rx_reg;
unsigned int reg_width;
};
void txx9_dmac_init(int id, unsigned long baseaddr, int irq,
const struct txx9dmac_platform_data *pdata);
#endif /* __ASM_TXX9_DMAC_H */
|
