1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x80000000 0x00010000;
/ {
compatible = "fsl,s32v234";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80000000>;
next-level-cache = <&cluster0_l2_cache>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80000000>;
next-level-cache = <&cluster0_l2_cache>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80000000>;
next-level-cache = <&cluster1_l2_cache>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80000000>;
next-level-cache = <&cluster1_l2_cache>;
};
cluster0_l2_cache: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
cluster1_l2_cache: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
/* clock-frequency might be modified by u-boot, depending on the
* chip version.
*/
clock-frequency = <10000000>;
};
gic: interrupt-controller@7d001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x7d001000 0 0x1000>,
<0 0x7d002000 0 0x2000>,
<0 0x7d004000 0 0x2000>,
<0 0x7d006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
aips0: bus@40000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
reg = <0x0 0x40000000 0x0 0x7d000>;
ranges;
uart0: serial@40053000 {
compatible = "fsl,s32v234-linflexuart";
reg = <0x0 0x40053000 0x0 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};
aips1: bus@40080000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
reg = <0x0 0x40080000 0x0 0x70000>;
ranges;
uart1: serial@400bc000 {
compatible = "fsl,s32v234-linflexuart";
reg = <0x0 0x400bc000 0x0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};
};
};
|
