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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree fragment for LS1028A QDS board, serdes 7777
*
* Copyright 2019-2021 NXP
*
* Requires a LS1028A QDS board without lane B rework.
* Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
* disabled, plugged in slot 1.
*/
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&mdio_slot1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
/* 4 ports on AQR412 */
slot1_sxgmii0: ethernet-phy@0 {
reg = <0x0>;
compatible = "ethernet-phy-ieee802.3-c45";
};
slot1_sxgmii1: ethernet-phy@1 {
reg = <0x1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
slot1_sxgmii2: ethernet-phy@2 {
reg = <0x2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
slot1_sxgmii3: ethernet-phy@3 {
reg = <0x3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
};
fragment@1 {
target = <&mscc_felix_ports>;
__overlay__ {
port@0 {
status = "okay";
phy-handle = <&slot1_sxgmii0>;
phy-mode = "2500base-x";
};
port@1 {
status = "okay";
phy-handle = <&slot1_sxgmii1>;
phy-mode = "2500base-x";
};
port@2 {
status = "okay";
phy-handle = <&slot1_sxgmii2>;
phy-mode = "2500base-x";
};
port@3 {
status = "okay";
phy-handle = <&slot1_sxgmii3>;
phy-mode = "2500base-x";
};
};
};
fragment@2 {
target = <&mscc_felix>;
__overlay__ {
status = "okay";
};
};
};
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