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/*
* Copyright 2012 Stefan Roese <sr@denx.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
compatible = "st,spear600";
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xd0000000 0xd0000000 0x30000000>;
vic0: interrupt-controller@f1100000 {
compatible = "arm,pl190-vic";
interrupt-controller;
reg = <0xf1100000 0x1000>;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@f1000000 {
compatible = "arm,pl190-vic";
interrupt-controller;
reg = <0xf1000000 0x1000>;
#interrupt-cells = <1>;
};
dma@fc400000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0xfc400000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <10>;
status = "disabled";
};
gmac: ethernet@e0800000 {
compatible = "st,spear600-gmac";
reg = <0xe0800000 0x8000>;
interrupt-parent = <&vic1>;
interrupts = <24 23>;
interrupt-names = "macirq", "eth_wake_irq";
status = "disabled";
};
fsmc: flash@d1800000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd1800000 0x1000 /* FSMC Register */
0xd2000000 0x4000>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
status = "disabled";
};
smi: flash@fc000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xfc000000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <12>;
status = "disabled";
};
ehci@e1800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe1800000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <27>;
status = "disabled";
};
ehci@e2000000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe2000000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <29>;
status = "disabled";
};
ohci@e1900000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe1900000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <26>;
status = "disabled";
};
ohci@e2100000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe2100000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <28>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xd0000000 0xd0000000 0x30000000>;
serial@d0000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xd0000000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <24>;
status = "disabled";
};
serial@d0080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xd0080000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <25>;
status = "disabled";
};
/* local/cpu GPIO */
gpio0: gpio@f0100000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xf0100000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <18>;
};
/* basic GPIO */
gpio1: gpio@fc980000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xfc980000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <19>;
};
/* appl GPIO */
gpio2: gpio@d8100000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xd8100000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <4>;
};
i2c@d0200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xd0200000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <28>;
status = "disabled";
};
timer@f0000000 {
compatible = "st,spear-timer";
reg = <0xf0000000 0x400>;
interrupt-parent = <&vic0>;
interrupts = <16>;
};
};
};
};
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