1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
*
* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
*
* Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/microchip,lan966x.h>
/ {
model = "Microchip LAN966 family SoC";
compatible = "microchip,lan966";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <600000000>;
reg = <0x0>;
};
};
clocks {
sys_clk: sys_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <162500000>;
};
cpu_clk: cpu_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
ddr_clk: ddr_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
nic_clk: nic_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
};
clks: clock-controller@e00c00a8 {
compatible = "microchip,lan966x-gck";
#clock-cells = <1>;
clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
clock-names = "cpu", "ddr", "sys";
reg = <0xe00c00a8 0x38>;
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <37500000>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
flx0: flexcom@e0040000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe0040000 0x100>;
clocks = <&clks GCK_ID_FLEXCOM0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0040000 0x800>;
status = "disabled";
};
flx1: flexcom@e0044000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe0044000 0x100>;
clocks = <&clks GCK_ID_FLEXCOM1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0044000 0x800>;
status = "disabled";
};
trng: rng@e0048000 {
compatible = "atmel,at91sam9g45-trng";
reg = <0xe0048000 0x100>;
clocks = <&nic_clk>;
};
aes: crypto@e004c000 {
compatible = "atmel,at91sam9g46-aes";
reg = <0xe004c000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
<&dma0 AT91_XDMAC_DT_PERID(12)>;
dma-names = "rx", "tx";
clocks = <&nic_clk>;
clock-names = "aes_clk";
};
flx2: flexcom@e0060000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe0060000 0x100>;
clocks = <&clks GCK_ID_FLEXCOM2>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0060000 0x800>;
status = "disabled";
};
flx3: flexcom@e0064000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe0064000 0x100>;
clocks = <&clks GCK_ID_FLEXCOM3>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0064000 0x800>;
status = "disabled";
usart3: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&nic_clk>;
clock-names = "usart";
atmel,fifo-size = <32>;
status = "disabled";
};
};
dma0: dma-controller@e0068000 {
compatible = "microchip,sama7g5-dma";
reg = <0xe0068000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&nic_clk>;
clock-names = "dma_clk";
};
sha: crypto@e006c000 {
compatible = "atmel,at91sam9g46-sha";
reg = <0xe006c000 0xec>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
dma-names = "tx";
clocks = <&nic_clk>;
clock-names = "sha_clk";
};
flx4: flexcom@e0070000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe0070000 0x100>;
clocks = <&clks GCK_ID_FLEXCOM4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0070000 0x800>;
status = "disabled";
};
timer0: timer@e008c000 {
compatible = "snps,dw-apb-timer";
reg = <0xe008c000 0x400>;
clocks = <&nic_clk>;
clock-names = "timer";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@e0090000 {
compatible = "snps,dw-wdt";
reg = <0xe0090000 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&nic_clk>;
status = "disabled";
};
can0: can@e081c000 {
compatible = "bosch,m_can";
reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
clock-names = "hclk", "cclk";
assigned-clocks = <&clks GCK_ID_MCAN0>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
status = "disabled";
};
gpio: pinctrl@e2004064 {
compatible = "microchip,lan966x-pinctrl";
reg = <0xe2004064 0xb4>,
<0xe2010024 0x138>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 78>;
interrupt-controller;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
gic: interrupt-controller@e8c11000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
reg = <0xe8c11000 0x1000>,
<0xe8c12000 0x2000>,
<0xe8c14000 0x2000>,
<0xe8c16000 0x2000>;
};
};
};
|
