blob: 8231dde2bfa602d0ebc0e1ec1e01c2d15856e8ad (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/intel,keembay-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Keem Bay SoC non-secure Watchdog Timer
maintainers:
- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
enum:
- intel,keembay-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
items:
- description: interrupt specifier for threshold interrupt line
- description: interrupt specifier for timeout interrupt line
interrupt-names:
items:
- const: threshold
- const: timeout
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define KEEM_BAY_A53_TIM
watchdog: watchdog@2033009c {
compatible = "intel,keembay-wdt";
reg = <0x2033009c 0x10>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "threshold", "timeout";
clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
};
...
|
