blob: 2d5b2ad03314bc7ea2b03cc5209d68db4ebc6258 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
Qualcomm QPNP PMIC Temperature Alarm
QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips
that utilize the Qualcomm SPMI implementation. These peripherals provide an
interrupt signal and status register to identify high PMIC die temperature.
Required properties:
- compatible: Should contain "qcom,spmi-temp-alarm".
- reg: Specifies the SPMI address.
- interrupts: PMIC temperature alarm interrupt.
- #thermal-sensor-cells: Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
Optional properties:
- io-channels: Should contain IIO channel specifier for the ADC channel,
which report chip die temperature.
- io-channel-names: Should contain "thermal".
Example:
pm8941_temp: thermal-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <0>;
io-channels = <&pm8941_vadc VADC_DIE_TEMP>;
io-channel-names = "thermal";
};
thermal-zones {
pm8941 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&pm8941_temp>;
trips {
stage1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
stage2 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
|
