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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC7180 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
properties:
compatible:
const: qcom,sc7180-pinctrl
reg:
maxItems: 3
reg-names:
items:
- const: west
- const: north
- const: south
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 60
gpio-line-names:
maxItems: 119
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sc7180-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sc7180-tlmm-state"
additionalProperties: false
$defs:
qcom-sc7180-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
atest_char1, atest_char2, atest_char3, atest_tsens,
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
_V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
required:
- pins
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
- reg-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@3500000 {
compatible = "qcom,sc7180-pinctrl";
reg = <0x03500000 0x300000>,
<0x03900000 0x300000>,
<0x03d00000 0x300000>;
reg-names = "west", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 120>;
wakeup-parent = <&pdc>;
dp_hot_plug_det: dp-hot-plug-det-state {
pins = "gpio117";
function = "dp_hot";
};
qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
spi-pins {
pins = "gpio53", "gpio54", "gpio55";
function = "qup15";
};
cs-pins {
pins = "gpio56";
function = "gpio";
};
};
};
|
