1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm QUSB2 phy controller
maintainers:
- Manu Gautam <mgautam@codeaurora.org>
description:
QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,ipq8074-qusb2-phy
- qcom,msm8953-qusb2-phy
- qcom,msm8996-qusb2-phy
- qcom,msm8998-qusb2-phy
- qcom,qcm2290-qusb2-phy
- qcom,sdm660-qusb2-phy
- qcom,ipq6018-qusb2-phy
- qcom,sm4250-qusb2-phy
- qcom,sm6115-qusb2-phy
- items:
- enum:
- qcom,sc7180-qusb2-phy
- qcom,sdm845-qusb2-phy
- qcom,sm6350-qusb2-phy
- const: qcom,qusb2-v2-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
clocks:
minItems: 2
items:
- description: phy config clock
- description: 19.2 MHz ref clk
- description: phy interface clock (Optional)
clock-names:
minItems: 2
items:
- const: cfg_ahb
- const: ref
- const: iface
vdd-supply:
description:
Phandle to 0.9V regulator supply to PHY digital circuit.
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
vdda-phy-dpdm-supply:
description:
Phandle to 3.1V regulator supply to Dp/Dm port signals.
resets:
maxItems: 1
description:
Phandle to reset to phy block.
nvmem-cells:
maxItems: 1
description:
Phandle to nvmem cell that contains 'HS Tx trim'
tuning parameter value for qusb2 phy.
qcom,tcsr-syscon:
description:
Phandle to TCSR syscon register region.
$ref: /schemas/types.yaml#/definitions/phandle
if:
properties:
compatible:
contains:
const: qcom,qusb2-v2-phy
then:
properties:
qcom,imp-res-offset-value:
description:
It is a 6 bit value that specifies offset to be
added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
tuning parameter that may vary for different boards of same SOC.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 63
default: 0
qcom,bias-ctrl-value:
description:
It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
tuning parameter that may vary for different boards of same SOC.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 63
default: 32
qcom,charge-ctrl-value:
description:
It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
tuning parameter that may vary for different boards of same SOC.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
default: 0
qcom,hstx-trim-value:
description:
It is a 4 bit value that specifies tuning for HSTX
output current.
Possible range is - 15mA to 24mA (stepsize of 600 uA).
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
default: 3
qcom,preemphasis-level:
description:
It is a 2 bit value that specifies pre-emphasis level.
Possible range is 0 to 15% (stepsize of 5%).
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
default: 2
qcom,preemphasis-width:
description:
It is a 1 bit value that specifies how long the HSTX
pre-emphasis (specified using qcom,preemphasis-level) must be in
effect. Duration could be half-bit of full-bit.
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1
default: 0
qcom,hsdisc-trim-value:
description:
It is a 2 bit value tuning parameter that control disconnect
threshold and may vary for different boards of same SOC.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
default: 0
required:
- compatible
- reg
- "#phy-cells"
- clocks
- clock-names
- vdd-supply
- vdda-pll-supply
- vdda-phy-dpdm-supply
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
hsusb_phy: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x7411000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX1_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
vdd-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
vdda-phy-dpdm-supply = <&pm8994_l24>;
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
};
|
