blob: 445b2467f4f6be049f074fc78f51c528f284da96 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: NVIDIA Tegra194 & Tegra234 P2U
maintainers:
- Thierry Reding <treding@nvidia.com>
description: >
Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
Speed) each interfacing with 12 and 8 P2U instances respectively.
Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
each interfacing with 8, 8 and 8 P2U instances respectively.
A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
PCIe lane.
properties:
compatible:
enum:
- nvidia,tegra194-p2u
- nvidia,tegra234-p2u
reg:
maxItems: 1
description: Should be the physical address space and length of respective each P2U instance.
reg-names:
items:
- const: ctl
nvidia,skip-sz-protect-en:
description: Should be present if two PCIe retimers are present between
the root port and its immediate downstream device.
type: boolean
'#phy-cells':
const: 0
additionalProperties: false
examples:
- |
p2u_hsio_0: phy@3e10000 {
compatible = "nvidia,tegra194-p2u";
reg = <0x03e10000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
|