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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/samsung,exynos4210-csis.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
properties:
compatible:
enum:
- samsung,s5pv210-csis
- samsung,exynos4210-csis
- samsung,exynos4212-csis
- samsung,exynos5250-csis
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
bus-width:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4]
description:
Number of data lines supported.
clocks:
maxItems: 2
clock-names:
items:
- const: csis
- const: sclk_csis
clock-frequency:
default: 166000000
description:
The IP's main (system bus) clock frequency in Hz.
interrupts:
maxItems: 1
phys:
maxItems: 1
phy-names:
items:
- const: csis
power-domains:
maxItems: 1
vddio-supply:
description: MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V).
vddcore-supply:
description: MIPI CSIS Core voltage supply (e.g. 1.1V).
patternProperties:
"^port@[34]$":
$ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
description:
Camera input port.
properties:
reg:
enum: [3, 4]
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
samsung,csis-hs-settle:
$ref: /schemas/types.yaml#/definitions/uint32
description: Differential receiver (HS-RX) settle time.
samsung,csis-wclk:
type: boolean
description:
CSI-2 wrapper clock selection. If this property is present external clock
from CMU will be used, or the bus clock if it's not specified.
required:
- data-lanes
required:
- reg
required:
- compatible
- reg
- bus-width
- clocks
- clock-names
- interrupts
- vddio-supply
- vddcore-supply
anyOf:
- required:
- port@3
- required:
- port@4
allOf:
- if:
required:
- samsung,isp-wb
then:
required:
- samsung,sysreg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
csis@11890000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11890000 0x4000>;
clocks = <&clock CLK_CSIS1>,
<&clock CLK_SCLK_CSIS1>;
clock-names = "csis", "sclk_csis";
assigned-clocks = <&clock CLK_MOUT_CSIS1>,
<&clock CLK_SCLK_CSIS1>;
assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
assigned-clock-rates = <0>, <176000000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <2>;
power-domains = <&pd_cam>;
phys = <&mipi_phy 2>;
phy-names = "csis";
vddcore-supply = <&ldo8_reg>;
vddio-supply = <&ldo10_reg>;
#address-cells = <1>;
#size-cells = <0>;
/* Camera D (4) MIPI CSI-2 (CSIS1) */
port@4 {
reg = <4>;
endpoint {
remote-endpoint = <&is_s5k6a3_ep>;
data-lanes = <1>;
samsung,csis-hs-settle = <18>;
samsung,csis-wclk;
};
};
};
|
