blob: 25dbb0fac0656460eeda590792abe9e7227ebfe9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1D (R9A06G032) System Controller
maintainers:
- Gareth Williams <gareth.williams.jx@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
const: renesas,r9a06g032-sysctrl
reg:
maxItems: 1
clocks:
minItems: 1
items:
- description: External 40 MHz crystal
- description: Optional external 32.768 kHz crystal
- description: Optional external JTAG input
- description: Optional external RGMII_REFCLK
clock-names:
minItems: 1
items:
- const: mclk
- const: rtc
- const: jtag
- const: rgmii_ref_ext
'#clock-cells':
const: 1
'#power-domain-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
sysctrl: system-controller@4000c000 {
compatible = "renesas,r9a06g032-sysctrl";
reg = <0x4000c000 0x1000>;
clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>,
<&ext_rgmii_ref>;
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
#clock-cells = <1>;
#power-domain-cells = <0>;
};
|