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path: root/sound/soc/fsl/fsl_sai.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-06ASoC: fsl_sai: fix 1:1 bclk:mclk ratio supportAhmad Fatoum1-1/+1
2022-03-07ASoC: fsl_sai: implement 1:1 bclk:mclk ratio supportAhmad Fatoum1-2/+15
2022-03-07ASoC: fsl_sai: use DIV_ROUND_CLOSEST() to calculate dividerSascha Hauer1-7/+5
2022-03-07ASoC: fsl_sai: Use better variable namesSascha Hauer1-8/+9
2022-03-07ASoC: fsl_sai: store full version instead of major/minorSascha Hauer1-5/+3
2022-03-07ASoC: fsl_sai: simplify register poking in fsl_sai_set_bclkAhmad Fatoum1-16/+13
2022-03-07ASoC: fsl_sai: simplify irq return valueSascha Hauer1-7/+4
2022-03-07ASoC: fsl_sai: Drop unnecessary definesSascha Hauer1-10/+6
2022-02-28ASoC: fsl: Drop unused argument from imx_pcm_dma_init()Sascha Hauer1-1/+1
2022-02-08ASoC: fsl_sai: Enable combine mode softSascha Hauer1-0/+9
2021-09-22ASoC: fsl_sai: Update to modern clocking terminologyMark Brown1-17/+17
2021-09-10ASoC: fsl_sai: register platform component before registering cpu daiShengjiu Wang1-5/+9
2021-06-21ASoC: fsl_sai: Use devm_platform_get_and_ioremap_resource()Yang Yingliang1-2/+1
2021-03-22ASoC: fsl_sai: Don't use devm_regmap_init_mmio_clkShengjiu Wang1-16/+32
2021-03-10Merge series "drop unneeded snd_soc_dai_set_drvdata" from Julia Lawall <Julia...Mark Brown1-2/+0
2021-03-10ASoC: fsl_sai: Add pm qos cpu latency supportShengjiu Wang1-0/+12
2021-03-10ASoC: fsl: drop unneeded snd_soc_dai_set_drvdataJulia Lawall1-2/+0
2021-01-21ASoC: fsl: sync parameter naming (rate/sample_bits)Kuninori Morimoto1-4/+4
2020-11-19ASoC: fsl_sai: Correct the clock source for mclk0Shengjiu Wang1-2/+18
2020-10-09Merge remote-tracking branch 'asoc/for-5.10' into asoc-nextMark Brown1-91/+199
2020-09-25ASoC: fsl_sai: Instantiate snd_soc_dai_driverShengjiu Wang1-8/+11
2020-09-17ASoC: fsl_sai: Set MCLK input or output directionShengjiu Wang1-0/+7
2020-09-17ASoC: fsl_sai: Add fsl_sai_check_version functionShengjiu Wang1-0/+47
2020-09-17ASoC: fsl_sai: Add new added registers and new bit definitionShengjiu Wang1-0/+23
2020-09-03ASoC: fsl_sai: Set SAI Channel Mode to Output ModeShengjiu Wang1-2/+8
2020-09-03ASoC: fsl_sai: Support multiple data channel enable bitsShengjiu Wang1-18/+12
2020-08-24ASoC: fsl_sai: Add -EPROBE_DEFER check for regmap initShengjiu Wang1-1/+1
2020-08-17ASoC: fsl_sai: Replace synchronous check with fsl_sai_dir_is_syncedShengjiu Wang1-24/+16
2020-08-17ASoC: fsl_sai: Drop TMR/RMR settings for synchronous modeShengjiu Wang1-6/+1
2020-08-17ASoC: fsl_sai: Refine enable/disable TE/RE sequence in trigger()Shengjiu Wang1-41/+85
2020-07-31Merge remote-tracking branch 'asoc/for-5.9' into asoc-nextMark Brown1-1/+2
2020-07-31ASoC: fsl_sai: Fix value of FSL_SAI_CR1_RFW_MASKShengjiu Wang1-2/+3
2020-07-01ASoC: fsl_sai: Refine regcache usage with pm runtimeShengjiu Wang1-1/+2
2020-02-06ASoC: fsl_sai: Fix exiting path on probing failureOleksandr Suvorov1-5/+17
2019-12-09ASoC: fsl_sai: add IRQF_SHAREDMichael Walle1-1/+2
2019-09-17ASoC: fsl_sai: Fix noise when using EDMAMihai Serban1-0/+15
2019-09-13ASoC: fsl_sai: Implement set_bclk_ratioViorel Suman1-2/+19
2019-08-21ASoC: fsl_sai: Add support for imx8qmDaniel Baluta1-0/+7
2019-08-07ASoC: fsl_sai: Add support for imx7ulp/imx8mqDaniel Baluta1-0/+14
2019-08-07ASoC: fsl_sai: Add support for SAI new versionDaniel Baluta1-93/+135
2019-08-07ASoC: fsl_sai: Update Tx/Rx channel enable maskDaniel Baluta1-2/+4
2019-08-07ASoC: fsl_sai: Add registers definition for multiple datalinesDaniel Baluta1-10/+66
2019-08-02ASoC: Remove dev_err() usage after platform_get_irq()Stephen Boyd1-3/+1
2019-07-22ASoC: fsl_sai: mark regmap as fast_ioLucas Stach1-0/+1
2019-07-22ASoC: fsl_sai: derive TX FIFO watermark from FIFO depthLucas Stach1-1/+3
2019-07-22ASoC: fsl_sai: add of_match dataLucas Stach1-8/+14
2019-05-08ASoC: fsl_sai: Move clock operation to PM runtimeShengjiu Wang1-10/+44
2019-04-26ASoC: fsl_sai: Add missing return 0 in remove()Nicolin Chen1-0/+2
2019-04-25ASoC: fsl_sai: Add support for runtime pmDaniel Baluta1-5/+17
2019-04-25ASoC: fsl_sai: Update is_slave_mode with correct valueDaniel Baluta1-0/+2
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