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path: root/sound/soc/fsl/fsl_sai.c
AgeCommit message (Expand)AuthorFilesLines
2023-07-27ASoC: fsl_sai: Revert "ASoC: fsl_sai: Enable MCTL_MCLK_EN bit for master mode"Fabio Estevam1-6/+0
2023-07-27ASoC: fsl_sai: Disable bit clock with transmitterMatus Gajdos1-1/+1
2023-06-28ASoC: fsl_sai: Enable BCI bit if SAI works on synchronous mode with BYP assertedChancel Liu1-2/+9
2023-04-26ASoC: fsl_sai: Fix pins setting for i.MX8QM platformChancel Liu1-1/+1
2023-03-10ASoC: fsl_sai: initialize is_dsp_mode flagShengjiu Wang1-0/+1
2023-02-14ASoC: fsl_sai: fix getting version from VERIDShengjiu Wang1-0/+1
2022-10-28ASoC: fsl_asrc fsl_esai fsl_sai: allow CONFIG_PM=NMaarten Zanders1-1/+1
2022-08-23ASoC: fsl_sai: Update slots number according to bclk_ratioShengjiu Wang1-3/+5
2022-08-23ASoC: fsl_sai: Add support multi fifo sdma scriptShengjiu Wang1-1/+36
2022-08-17ASoC: fsl_sai: Remove unnecessary FIFO reset in ISRShengjiu Wang1-8/+2
2022-08-16ASoC: fsl_sai: fix incorrect mclk number in error messagePieterjan Camerlynck1-1/+1
2022-07-21ASoC: fsl_sai: Don't use plain integer as NULL pointerShengjiu Wang1-1/+1
2022-07-05ASoC: fsl_sai: Add support for PLL switch at runtimeShengjiu Wang1-0/+38
2022-06-29ASoC: Refactor non_legacy_dai_naming flagMark Brown1-2/+3
2022-06-28Add PDM/DSD/dataline configuration supportMark Brown1-21/+239
2022-06-27ASoC: fsl_sai: Configure dataline/FIFO information from dts propertyShengjiu Wang1-4/+157
2022-06-27ASoC: fsl_sai: Make res a member of struct fsl_saiShengjiu Wang1-4/+3
2022-06-27ASoc: fsl_sai: Add pinctrl operation for PDM and DSDShengjiu Wang1-9/+61
2022-06-27ASoC: fsl_sai: Add support for more sample ratesShengjiu Wang1-3/+4
2022-06-27ASoC: fsl_sai: Add PDM daifmt supportShengjiu Wang1-2/+15
2022-06-27ASoC: fsl: fsl_sai: use pm_runtime_resume_and_get()Pierre-Louis Bossart1-4/+2
2022-06-27ASoC: fsl: Migrate to new style legacy DAI naming flagCharles Keepax1-1/+2
2022-06-14ASoC: Merge fixesMark Brown1-0/+1
2022-06-09Specify clock provider directly to CPU DAIsMark Brown1-4/+4
2022-06-08ASoC: fsl_sai: Enable MCTL_MCLK_EN bit for master modeShengjiu Wang1-0/+6
2022-06-06ASoC: fsl_sai: add error message in case of missing imx-pcm-dma supportMarco Felsch1-1/+4
2022-06-06ASoC: fsl_sai: use local device pointerMarco Felsch1-26/+27
2022-06-06ASoC: fsl: Rename set_fmt_new back to set_fmtCharles Keepax1-1/+1
2022-06-06ASoC: fsl: Update to use set_fmt_new callbackCharles Keepax1-5/+5
2022-06-06ASoC: fsl_sai: Add support for i.MX8MNShengjiu Wang1-0/+1
2022-05-16ASoC: fsl_sai: Add support for i.MX8ULPShengjiu Wang1-1/+13
2022-05-16ASoC: fsl_sai: Add support for i.MX8M PlusShengjiu Wang1-0/+12
2022-05-16ASoC: fsl_sai: Add support for i.MX8MMShengjiu Wang1-0/+17
2022-04-06ASoC: fsl_sai: fix 1:1 bclk:mclk ratio supportAhmad Fatoum1-1/+1
2022-03-07ASoC: fsl_sai: implement 1:1 bclk:mclk ratio supportAhmad Fatoum1-2/+15
2022-03-07ASoC: fsl_sai: use DIV_ROUND_CLOSEST() to calculate dividerSascha Hauer1-7/+5
2022-03-07ASoC: fsl_sai: Use better variable namesSascha Hauer1-8/+9
2022-03-07ASoC: fsl_sai: store full version instead of major/minorSascha Hauer1-5/+3
2022-03-07ASoC: fsl_sai: simplify register poking in fsl_sai_set_bclkAhmad Fatoum1-16/+13
2022-03-07ASoC: fsl_sai: simplify irq return valueSascha Hauer1-7/+4
2022-03-07ASoC: fsl_sai: Drop unnecessary definesSascha Hauer1-10/+6
2022-02-28ASoC: fsl: Drop unused argument from imx_pcm_dma_init()Sascha Hauer1-1/+1
2022-02-08ASoC: fsl_sai: Enable combine mode softSascha Hauer1-0/+9
2021-09-22ASoC: fsl_sai: Update to modern clocking terminologyMark Brown1-17/+17
2021-09-10ASoC: fsl_sai: register platform component before registering cpu daiShengjiu Wang1-5/+9
2021-06-21ASoC: fsl_sai: Use devm_platform_get_and_ioremap_resource()Yang Yingliang1-2/+1
2021-03-22ASoC: fsl_sai: Don't use devm_regmap_init_mmio_clkShengjiu Wang1-16/+32
2021-03-10Merge series "drop unneeded snd_soc_dai_set_drvdata" from Julia Lawall <Julia...Mark Brown1-2/+0
2021-03-10ASoC: fsl_sai: Add pm qos cpu latency supportShengjiu Wang1-0/+12
2021-03-10ASoC: fsl: drop unneeded snd_soc_dai_set_drvdataJulia Lawall1-2/+0
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