starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-12-05	soc: fsl: qe: request pins non-exclusively	Dmitry Torokhov	1	-2/+3
2021-04-06	Revert "soc: fsl: qe: introduce qe_io{read,write}* wrappers"	Christophe Leroy	1	-25/+9
2021-01-21	ethernet: ucc_geth: remove bd_mem_part and all associated code	Rasmus Villemoes	1	-6/+0
2021-01-21	soc: fsl: qe: add cpm_muram_free_addr() helper	Rasmus Villemoes	1	-0/+5
2021-01-21	soc: fsl: qe: make cpm_muram_offset take a const void* argument	Rasmus Villemoes	1	-2/+2
2020-05-23	soc: fsl: qe: Replace one-element array and use struct_size() helper	Gustavo A. R. Silva	1	-1/+1
2019-12-09	soc: fsl: qe: make cpm_muram_free() return void	Rasmus Villemoes	1	-3/+2
2019-12-09	soc: fsl: qe: change return type of cpm_muram_alloc() to s32	Rasmus Villemoes	1	-8/+8
2019-12-09	soc/fsl/qe/qe.h: update include path for cpm.h	Rasmus Villemoes	1	-1/+1
2019-12-09	soc: fsl: qe: introduce qe_io{read,write}* wrappers	Rasmus Villemoes	1	-9/+25
2019-12-09	soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers	Rasmus Villemoes	1	-9/+9
2019-07-17	docs: powerpc: convert docs to ReST and rename to *.rst	Mauro Carvalho Chehab	1	-1/+1
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152	Thomas Gleixner	1	-5/+1
2017-05-18	net/wan/fsl_ucc_hdlc: add hdlc-bus support	Holger Brunck	1	-0/+5
2017-05-18	fsl/qe: add bit description for SYNL register for GUMR	Holger Brunck	1	-0/+4
2017-04-30	net: ethernet: ucc_geth: fix MEM_PART_MURAM mode	Christophe Leroy	1	-0/+1
2016-06-08	drivers/net: support hdlc function for QE-UCC	Zhao Qiang	1	-0/+1
2016-06-08	fsl/qe: setup clock source for TDM mode	Zhao Qiang	1	-0/+16
2016-06-08	fsl/qe: add rx_sync and tx_sync for TDM mode	Zhao Qiang	1	-0/+2
2016-03-09	qe: Make cpm_muram_alloc_common static	Saurabh Sengar	1	-2/+0
2015-12-23	QE: Move QE from arch/powerpc to drivers/soc	Zhao Qiang	1	-0/+790