index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
include
/
soc
/
arc
Age
Commit message (
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)
Author
Files
Lines
2021-10-16
clocksource/drivers/arc_timer: Eliminate redefined macro error
Randy Dunlap
1
-2
/
+2
2020-08-12
include/: replace HTTP links with HTTPS ones
Alexander A. Klimov
1
-1
/
+1
2019-08-26
ARCv2: IDU-intc: Add support for edge-triggered interrupts
Mischa Jonker
1
-0
/
+11
2019-06-19
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
Thomas Gleixner
3
-13
/
+3
2018-02-28
ARC: mcip: update MCIP debug mask when the new cpu came online
Eugeniy Paltsev
1
-0
/
+2
2018-02-28
ARC: mcip: halt GFRC counter when ARC cores halt
Eugeniy Paltsev
1
-0
/
+3
2017-02-06
ARCv2: IDU-intc: Use build registers for getting numbers of interrupts
Yuriy Kolerov
1
-0
/
+17
2017-01-24
ARCv2: MCIP: update the BCR per current changes
Vineet Gupta
1
-8
/
+8
2016-11-30
ARC: breakout timer include code into separate header ...
Vineet Gupta
1
-0
/
+38
2016-11-30
ARC: move mcip.h into include/soc and adjust the includes
Vineet Gupta
1
-0
/
+103
2016-11-30
ARC: breakout aux handling into a separate header
Vineet Gupta
1
-0
/
+63