index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
spi
/
spi-dw-core.c
Age
Commit message (
Expand
)
Author
Files
Lines
2020-12-09
spi: dw: Add support for 32-bits max xfer size
Damien Le Moal
1
-7
/
+37
2020-11-25
spi: dw: Fix spi registration for controllers overriding CS
Lars Povlsen
1
-1
/
+2
2020-11-17
spi: dw: Set transfer handler before unmasking the IRQs
Serge Semin
1
-2
/
+2
2020-10-09
spi: dw: Add poll-based SPI transfers support
Serge Semin
1
-1
/
+39
2020-10-09
spi: dw: Introduce max mem-ops SPI bus frequency setting
Serge Semin
1
-1
/
+3
2020-10-09
spi: dw: Add memory operations support
Serge Semin
1
-0
/
+301
2020-10-09
spi: dw: Add generic DW SSI status-check method
Serge Semin
1
-9
/
+34
2020-10-09
spi: dw: Explicitly de-assert CS on SPI transfer completion
Serge Semin
1
-1
/
+1
2020-10-09
spi: dw: Discard chip enabling on DMA setup error
Serge Semin
1
-3
/
+1
2020-10-09
spi: dw: Unmask IRQs after enabling the chip
Serge Semin
1
-2
/
+2
2020-10-09
spi: dw: Perform IRQ setup in a dedicated function
Serge Semin
1
-18
/
+23
2020-10-09
spi: dw: Refactor IRQ-based SPI transfer procedure
Serge Semin
1
-9
/
+24
2020-10-09
spi: dw: Refactor data IO procedure
Serge Semin
1
-20
/
+17
2020-10-09
spi: dw: Add DW SPI controller config structure
Serge Semin
1
-12
/
+17
2020-10-09
spi: dw: Update Rx sample delay in the config function
Serge Semin
1
-7
/
+6
2020-10-09
spi: dw: Simplify the SPI bus speed config procedure
Serge Semin
1
-13
/
+10
2020-10-09
spi: dw: Update SPI bus speed in a config function
Serge Semin
1
-14
/
+14
2020-10-09
spi: dw: Detach SPI device specific CR0 config method
Serge Semin
1
-13
/
+30
2020-10-09
spi: dw: Add DWC SSI capability
Serge Semin
1
-43
/
+37
2020-10-09
spi: dw: Use an explicit set_cs assignment
Serge Semin
1
-4
/
+4
2020-09-29
spi: spi-dw: Remove extraneous locking
Serge Semin
1
-12
/
+2
2020-09-29
spi: dw: Add KeemBay Master capability
Serge Semin
1
-0
/
+4
2020-09-29
spi: dw: Convert CS-override to DW SPI capabilities
Serge Semin
1
-2
/
+2
2020-09-29
spi: dw: Discard DW SSI chip type storages
Serge Semin
1
-4
/
+2
2020-09-29
spi: dw: Disable all IRQs when controller is unused
Serge Semin
1
-5
/
+5
2020-09-29
spi: dw: Initialize n_bytes before the memory barrier
Serge Semin
1
-1
/
+1
2020-09-08
spi: dw: Add support for RX sample delay register
Lars Povlsen
1
-0
/
+26
2020-05-30
Merge remote-tracking branch 'spi/for-5.8' into spi-next
Mark Brown
1
-0
/
+545
2020-05-29
spi: dw: Use regset32 DebugFS method to create regdump file
Serge Semin
1
-60
/
+26
2020-05-29
spi: dw: Add core suffix to the DW APB SSI core source file
Serge Semin
1
-0
/
+577