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path: root/drivers/spi/Makefile
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2025-04-07spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controllerRaju Rangoju1-1/+1
Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-03-11spi: sophgo: add SG2044 SPI NOR controller driverLongbin Li1-0/+1
Add support for SG2044 SPI NOR controller in Sophgo SoC. Signed-off-by: Longbin Li <looong.bin@gmail.com> Link: https://patch.msgid.link/20250304083548.10101-3-looong.bin@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-03-04Add STM32MP25 SPI NOR supportMark Brown1-0/+1
Merge series from patrice.chotard@foss.st.com: This series adds SPI NOR support for STM32MP25 SoCs from STMicroelectronics. On STM32MP25 SoCs family, an Octo Memory Manager block manages the muxing, the memory area split, the chip select override and the time constraint between its 2 Octo SPI children. Due to these depedencies, this series adds support for: - Octo Memory Manager driver (not applied for SPI). - Octo SPI driver. - yaml schema for Octo Memory Manager and Octo SPI drivers. The device tree files adds Octo Memory Manager and its 2 associated Octo SPI chidren in stm32mp251.dtsi and adds SPI NOR support in stm32mp257f-ev1 board.
2025-03-03spi: spi-qpic: add driver for QCOM SPI NAND flash InterfaceMd Sadre Alam1-0/+1
This driver implements support for the SPI-NAND mode of QCOM NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20250224111414.2809669-3-quic_mdalam@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-03-03spi: stm32: Add OSPI driverPatrice Chotard1-0/+1
Add STM32 OSPI driver, it supports : - support sNOR / sNAND devices. - Three functional modes: indirect, automatic-status polling, memory-mapped. - Single-, dual-, quad-, and octal-SPI communication. - Dual-quad communication. - Single data rate (SDR). - DMA channel for indirect mode. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://patch.msgid.link/20250219080059.367045-3-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-02-07spi: offload-trigger: add PWM trigger driverDavid Lechner1-0/+3
Add a new driver for a generic PWM trigger for SPI offloads. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-4-e48a489be48c@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-02-07spi: add basic support for SPI offloadingDavid Lechner1-0/+1
Add the basic infrastructure to support SPI offload providers and consumers. SPI offloading is a feature that allows the SPI controller to perform transfers without any CPU intervention. This is useful, e.g. for high-speed data acquisition. SPI controllers with offload support need to implement the get_offload and put_offload callbacks and can use the devm_spi_offload_alloc() to allocate offload instances. SPI peripheral drivers will call devm_spi_offload_get() to get a reference to the matching offload instance. This offload instance can then be attached to a SPI message to request offloading that message. It is expected that SPI controllers with offload support will check for the offload instance in the SPI message in the ctlr->optimize_message() callback and handle it accordingly. CONFIG_SPI_OFFLOAD is intended to be a select-only option. Both consumer and provider drivers should `select SPI_OFFLOAD` in their Kconfig to ensure that the SPI core is built with offload support. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-1-e48a489be48c@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-04spi: spi-kspi2: Add KEBA SPI controller supportGerhard Engleder1-0/+1
The KEBA SPI controller is found in the system FPGA of KEBA PLC devices. It is used to connect the SPI flash chip of the FPGA and some SPI devices. It is a simple SPI controller with configurable speed. The hardware supports only single byte transfers. There are no FIFOs or interrupts. Signed-off-by: Gerhard Engleder <eg@keba.com> Link: https://patch.msgid.link/20241202194003.57679-1-gerhard@engleder-embedded.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-11-06spi: apple: Add driver for Apple SPI controllerHector Martin1-0/+1
This SPI controller is present in Apple SoCs such as the M1 (t8103) and M1 Pro/Max (t600x). It is a relatively straightforward design with two 16-entry FIFOs, arbitrary transfer sizes (up to 2**32 - 1) and fully configurable word size up to 32 bits. It supports one hardware CS line which can also be driven via the pinctrl/GPIO driver instead, if desired. TX and RX can be independently enabled. There are a surprising number of knobs for tweaking details of the transfer, most of which we do not use right now. Hardware CS control is available, but we haven't found a way to make it stay low across multiple logical transfers, so we just use software CS control for now. There is also a shared DMA offload coprocessor that can be used to handle larger transfers without requiring an IRQ every 8-16 words, but that feature depends on a bunch of scaffolding that isn't ready to be upstreamed yet, so leave it for later. The hardware shares some register bit definitions with spi-s3c24xx which suggests it has a shared legacy with Samsung SoCs, but it is too different to warrant sharing a driver. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Janne Grunau <j@jannau.net> Link: https://patch.msgid.link/20241106-asahi-spi-v5-2-e81a4f3a8e19@jannau.net Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-21spi: spi-mem: Add Realtek SPI-NAND controllerChris Packham1-0/+1
Add a driver for the SPI-NAND controller on the RTL9300 family of devices. The controller supports * Serial/Dual/Quad data with * PIO and DMA data read/write operation * Configurable flash access timing There is a separate ECC controller on the RTL9300 which isn't currently supported (instead we rely on the on-die ECC supported by most SPI-NAND chips). Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://patch.msgid.link/20241015225434.3970360-4-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown <broonie@kernel.org>
2024-07-08spi: add ch341a usb2spi driverJohannes Thumshirn1-0/+1
Add a driver for the QiHeng Electronics ch341a USB-to-SPI adapter. This driver is loosely based on the ch341a module from the flashrom project. Signed-off-by: Johannes Thumshirn <jth@kernel.org> Link: https://patch.msgid.link/20240708-spi-ch341a-v3-1-cf7f9b2c1e31@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-06-03spi: pxa2xx: Move platform driver to a separate fileAndy Shevchenko1-1/+2
The spi-pxa2xx.c is bloated with a platform driver code while pretending to provide a core functionality. Make it real core library by splitting out the platform driver to a separate file. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://msgid.link/r/20240530151117.1130792-11-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-04-30spi: airoha: add SPI-NAND Flash controller driverLorenzo Bianconi1-0/+1
Introduce support for SPI-NAND driver of the Airoha NAND Flash Interface found on Airoha ARM SoCs. Tested-by: Rajeev Kumar <Rajeev.Kumar@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/6c9db20505b01a66807995374f2af475a23ce5b2.1714377864.git.lorenzo@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2023-10-11spi: Add support for Intel LJCA USB SPI driverWentong Wu1-0/+1
Implements the SPI function of Intel USB-I2C/GPIO/SPI adapter device named "La Jolla Cove Adapter" (LJCA). It communicate with LJCA SPI module with specific protocol through interfaces exported by LJCA USB driver. Signed-off-by: Wentong Wu <wentong.wu@intel.com> Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/1696833205-16716-4-git-send-email-wentong.wu@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-19Add cs42l43 PC focused SoundWire CODECMark Brown1-0/+1
Merge series from Charles Keepax <ckeepax@opensource.cirrus.com>: This patch chain adds support for the Cirrus Logic cs42l43 PC focused SoundWire CODEC.
2023-08-18spi: cs42l43: Add SPI controller supportLucas Tanure1-0/+1
The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface (Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed for portable applications. It provides a high dynamic range, stereo DAC for headphone output, two integrated Class D amplifiers for loudspeakers, and two ADCs for wired headset microphone input or stereo line input. PDM inputs are provided for digital microphones. The SPI component incorporates a SPI controller interface for communication with other peripheral components. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230804104602.395892-6-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-31spi: loongson: add bus driver for the loongson spi controllerYinbo Zhu1-0/+3
This bus driver supports the Loongson SPI hardware controller in the Loongson platforms and supports the use DTS and PCI framework to register SPI device resources. Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Mark Brown <broonie@kernel.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230613075834.5219-3-zhuyinbo@loongson.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-23spi: Add support for Renesas CSIFabrizio Castro1-0/+1
The RZ/V2M SoC comes with the Clocked Serial Interface (CSI) IP, which is a master/slave SPI controller. This commit adds a driver to support CSI master mode. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/Message-Id: <20230622113341.657842-4-fabrizio.castro.jz@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-11spi: add support for Amlogic A1 SPI Flash ControllerMartin Kurbanov1-0/+1
This is a driver for the Amlogic SPI flash controller support on A113L SoC. Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230403183217.13280-3-mmkurbanov@sberdevices.ru Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-22Merge tag 'spi-v6.3' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "This has been a fairly quiet release for SPI, though it is likely that the next release will have some big changes as there's some preparatory work for multiple chip select support gone in - the rest of the code is on the list but will need to be rebased onto -rc1. Otherwise there's a couple of new tunables for chip select timings, some new devices and smaller device specific updates and fixes. - Support for configuring the hold and minimum inactive times for chip selects. - Beginnings of support for supporting devices which have multiple chip selects on a single device. - Support for newer Broadcom HSSPI and Intel controllers, Silicon Labs EM3581 and SI3210" * tag 'spi-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (67 commits) spi: dt-bindings: qcom,spi-qcom-qspi: document OPP and power-domains spi: spidev: drop the incorrect notice from Kconfig spi: bcm63xx-hsspi: fix error code in probe spi: bcmbca-hsspi: Fix error code in probe() function spi: synquacer: Fix timeout handling in synquacer_spi_transfer_one() spi: intel: Check number of chip selects after reading the descriptor spi: xilinx: add force_irq for QSPI mode spi: spi-st-ssc: convert to DT schema spi: Reorder fields in 'struct spi_transfer' spi: cadence-quadspi: use STIG mode for small reads spi: cadence-quadspi: setup ADDR Bits in cmd reads spi: cadence-quadspi: Add flag for direct mode writes spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion MAINTAINERS: Remove file reference for Broadcom Broadband SoC HS SPI driver entry spi: bcm63xx-hsspi: bcmbca-hsspi: fix _be16 type usage MAINTAINERS: Add entry for Broadcom Broadband SoC HS SPI drivers spi: bcmbca-hsspi: Add driver for newer HSSPI controller spi: bcm63xx-hsspi: Disable spi mem dual io read op support spi: spi-mem: Allow controller supporting mem_ops without exec_op spi: bcm63xx-hsspi: Add prepend mode support ...
2023-02-11spi: bcmbca-hsspi: Add driver for newer HSSPI controllerWilliam Zhang1-0/+1
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-01-16spi: remove s3c24xx driverArnd Bergmann1-2/+0
The s3c24xx platform was removed,s o there are no remaining users for its spi driver. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-01-12spi: remove omap 100K driverArnd Bergmann1-1/+0
The OMAP7xx/OMAP8xx support was removed since all of its boards have no remaining users. Remove its spi driver as well. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Janusz Krzysztofik <jmkrzyszt@gmail.com> Cc: linux-omap@vger.kernel.org Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: Fabrice Crohas <fcrohas@gmail.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-25spi: wpcm-fiu: Add driver for Nuvoton WPCM450 Flash Interface Unit (FIU)Jonathan Neuschäfer1-0/+1
The Flash Interface Unit (FIU) is the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The FIU in newer NPCM7xx SoCs is not compatible with the WPCM450 FIU. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221124191400.287918-3-j.neuschaefer@gmx.net Signed-off-by: Mark Brown <broonie@kernel.org>
2022-11-24spi: Add Socionext F_OSPI SPI flash controller driverKunihiko Hayashi1-0/+1
Introduce Socionext F_OSPI controller driver. This controller is used to communicate with slave devices such as SPI Flash memories. It supports 4 slave devices and up to 8-bit wide bus, but supports master mode only. This driver uses spi-mem framework for SPI flash memory access, and can only operate indirect access mode and single data rate mode. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221124003351.7792-3-hayashi.kunihiko@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switchTharun Kumar P1-0/+1
Microchip pci1xxxx is a PCIe switch with a multi-function endpoint on one of its downstream ports. SPI is one of the functions in the multi-function endpoint. This function has 2 SPI masters, operates at a maximum frequency of 30 MHz and supports 7 client devices per master. This patch adds complete functionality to the SPI function except for suspend and resume. Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Link: https://lore.kernel.org/r/20221006050514.115564-2-tharunkumar.pasumarthi@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: microchip-core-qspi: Add support for microchip fpga qspi controllersNaga Sureshkumar Relli1-0/+1
Add a driver for Microchip FPGA QSPI controllers. This driver also supports "hard" QSPI controllers on Polarfire SoC. Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220808064603.1174906-4-nagasuresh.relli@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-29spi: spi-gxp: Add support for HPE GXP SoCsNick Hawkins1-0/+1
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Link: https://lore.kernel.org/r/20220728161459.7738-2-nick.hawkins@hpe.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-07spi: add support for microchip fpga spi controllersConor Dooley1-0/+1
Add a driver for Microchip FPGA SPI controllers, specifically supporting the "hard" controllers on PolarFire SoC. Co-developed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220607073833.2331539-2-conor.dooley@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16spi: spi-mem: Convert Aspeed SMC driver to spi-memCédric Le Goater1-0/+1
This SPI driver adds support for the Aspeed static memory controllers of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface. * AST2600 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . Only supports SPI type flash memory . different segment register interface . single, dual and quad mode. * AST2600 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . different segment register interface . single, dual and quad mode. * AST2500 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver . single, dual mode. * AST2500 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . single, dual mode. * AST2400 New Static Memory Controller (also referred as FMC) . BMC firmware . New register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. . single, dual and quad mode. Each controller has a memory range on which flash devices contents are mapped. Each device is assigned a window that can be changed at bootime with the Segment Address Registers. Each SPI flash device can then be accessed in two modes: Command and User. When in User mode, SPI transfers are initiated with accesses to the memory segment of a device. When in Command mode, memory operations on the memory segment of a device generate SPI commands automatically using a Control Register for the settings. This initial patch adds support for User mode. Command mode needs a little more work to check that the memory window on the AHB bus fits the device size. It will come later when support for direct mapping is added. Single and dual mode RX transfers are supported. Other types than SPI are not supported. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-4-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-27spi: add driver for MTK SPI NAND Flash InterfaceChuanhong Guo1-0/+1
This driver implements support for the SPI-NAND mode of MTK NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Tested-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20220424032527.673605-3-gch981213@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-15mtd: spi-nor / spi / MFD: Convert intel-spi to SPI MEMMark Brown1-0/+3
Merge series from Mika Westerberg <mika.westerberg@linux.intel.com>: Based on discussion on the patch I sent some time ago here: http://lists.infradead.org/pipermail/linux-mtd/2021-June/086867.html it turns out that the preferred way to deal with the SPI flash controller drivers is through SPI MEM which is part of Linux SPI subsystem. This series does that for the intel-spi driver. This also renames the driver to follow the convention used in the SPI subsystem. The first patch improves the write protection handling to be slightly more safer. The following two patches do the conversion itself. Note the Intel SPI flash controller only allows commands such as read, write and so on and it internally uses whatever addressing etc. it figured from the SFDP on the flash device. base-commit: e783362eb54cd99b2cac8b3a9aeac942e6f6ac07
2022-02-14mtd: spi-nor: intel-spi: Convert to SPI MEMMika Westerberg1-0/+3
The preferred way to implement SPI-NOR controller drivers is through SPI subsubsystem utilizing the SPI MEM core functions. This converts the Intel SPI flash controller driver over the SPI MEM by moving the driver from SPI-NOR subsystem to SPI subsystem and in one go make it use the SPI MEM functions. The driver name will be changed from intel-spi to spi-intel to match the convention used in the SPI subsystem. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mauro Lima <mauro.lima@eclypsium.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220209122706.42439-3-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-01-25spi: Add spi driver for Sunplus SP7021Li-hao Kuo1-0/+1
Add spi driver for Sunplus SP7021. Signed-off-by: Li-hao Kuo <lhjeff911@gmail.com> Link: https://lore.kernel.org/r/37998e515d561e762ee30d0ac4fca25a948e0c5c.1642494310.git.lhjeff911@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-27spi: cadence: add support for Cadence XSPI controllerParshuram Thombare1-0/+1
This patch adds driver for Cadence's XSPI controller. It supports 3 work modes. 1. ACMD (auto command) work mode ACMD name is because it uses auto command engine in the controller. It further has 2 modes PIO and CDMA (command DMA). The CDMA work mode is dedicated for high-performance application where very low software overhead is required. In this mode the Command Engine is programmed by the series of linked descriptors stored in system memory. These descriptors provide commands to execute and store status information for finished commands. The PIO mode work mode is dedicated for single operation where constructing a linked list of descriptors would require too much effort. 2. STIG (Software Triggered Instruction Generator) work mode In STIG mode, controller sends low-level instructions to memory. Each instruction is 128-bit width. There is special instruction DataSequence which carries information about data phase. Driver uses Slave DMA interface to transfer data as only this interface can be used in STIG work mode. 3. Direct work mode This work mode allows sending data without invoking any command through the slave interface. Currently only STIG work mode is enabled, remaining work modes will be added later. Signed-off-by: Konrad Kociolek <konrad@cadence.com> Signed-off-by: Jayshri Pawar <jpawar@cadence.com> Signed-off-by: Parshuram Thombare <pthombar@cadence.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/1632038734-23999-1-git-send-email-pthombar@cadence.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-13SPI: add Ingenic JZ47xx driver.Artur Rojek1-0/+1
Add a driver to support the SPI controller found in Ingenic SoCs. Co-developed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Link: https://lore.kernel.org/r/20210830230139.21476-3-contact@artur-rojek.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2021-08-17spi: rockchip-sfc: add rockchip serial flash controllerChris Morgan1-0/+1
Add the rockchip serial flash controller (SFC) driver. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20210812134546.31340-3-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-04-20spi: altera: Add DFL bus driver for Altera API ControllerMatthew Gerlach1-0/+1
This patch adds a Device Feature List (DFL) bus driver for the Altera SPI Master controller. The SPI master is connected to an Intel SPI Slave to Avalon Bridge inside an Intel MAX10 BMC Chip. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Link: https://lore.kernel.org/r/20210416165720.554144-3-matthew.gerlach@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-04-20spi: altera: separate core code from platform codeMatthew Gerlach1-1/+2
In preparation of adding support for a new bus type, separate the core spi-altera code from the platform driver code. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Link: https://lore.kernel.org/r/20210416165720.554144-2-matthew.gerlach@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-03-31spi: Add HiSilicon SPI Controller Driver for Kunpeng SoCsJay Fang1-0/+1
This driver supports SPI Controller for HiSilicon Kunpeng SoCs. This driver supports SPI operations using FIFO mode of transfer. DMA is not supported, and we just use IRQ mode for operation completion notification. Only ACPI firmware is supported. Signed-off-by: Jay Fang <f.fangjian@huawei.com> Link: https://lore.kernel.org/r/1616836200-45827-1-git-send-email-f.fangjian@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-02-04spi: realtek-rtl: Add support for Realtek RTL838x/RTL839x SPI controllersBert Vermeulen1-0/+1
This driver likely also supports earlier (RTL8196) and later (RTL93xx) SoCs. The SPI hardware in these SoCs is specifically intended for connecting NOR bootflash chips, and only used for that in dozens of examined devices. However boiled down to basics, it's really just a half-duplex SPI controller. The hardware appears to have a vestigial second chip-select control, but it hasn't been seen in the wild and is thus not supported. Signed-off-by: Bert Vermeulen <bert@biot.com> Link: https://lore.kernel.org/r/20210120135928.246054-3-bert@biot.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-21spi: remove sirf prima/atlas driverArnd Bergmann1-1/+0
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120161658.3820610-1-arnd@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-15Merge series "Remove ARM platform efm32" from Uwe Kleine-König ↵Mark Brown1-1/+0
<u.kleine-koenig@pengutronix.de> Uwe Kleine-König <uwe.kleine-koenig@pengutronix.de>: From: Uwe Kleine-König <uwe.kleine-koenig@pengutronix.de> Hello, there are no known active users of the efm32 platform. Given that the only machine that is supported has only 4 MiB of RAM its use is also quite limited. Back then it served as the platform to develop ARMv7-M support in Linux which was quite fun and still is a blissful memory. Still given that the code serves no purpose and this probably won't change anytime soon, remove all platform support. I'm unsure what to do with the device tree bindings. Should we delete them, too? Best regards Uwe Uwe Kleine-König (7): ARM: drop efm32 platform clk: Drop unused efm32gg driver clocksource: Drop unused efm32 timer code spi: Drop unused efm32 bus driver i2c: Drop unused efm32 bus driver tty: Drop unused efm32 serial driver MAINTAINERS: Remove deleted platform efm32 MAINTAINERS | 7 - arch/arm/Kconfig | 10 +- arch/arm/Kconfig.debug | 17 - arch/arm/Makefile | 1 - arch/arm/boot/dts/Makefile | 2 - arch/arm/boot/dts/efm32gg-dk3750.dts | 88 --- arch/arm/boot/dts/efm32gg.dtsi | 177 ----- arch/arm/configs/efm32_defconfig | 98 --- arch/arm/include/debug/efm32.S | 45 -- arch/arm/mach-efm32/Makefile | 2 - arch/arm/mach-efm32/Makefile.boot | 4 - arch/arm/mach-efm32/dtmachine.c | 16 - arch/arm/mm/Kconfig | 1 - drivers/clk/Makefile | 1 - drivers/clk/clk-efm32gg.c | 84 --- drivers/clocksource/Kconfig | 9 - drivers/clocksource/Makefile | 1 - drivers/clocksource/timer-efm32.c | 278 -------- drivers/i2c/busses/Kconfig | 7 - drivers/i2c/busses/Makefile | 1 - drivers/i2c/busses/i2c-efm32.c | 469 ------------- drivers/spi/Kconfig | 7 - drivers/spi/Makefile | 1 - drivers/spi/spi-efm32.c | 462 ------------ drivers/tty/serial/Kconfig | 13 - drivers/tty/serial/Makefile | 1 - drivers/tty/serial/efm32-uart.c | 852 ----------------------- include/linux/platform_data/efm32-spi.h | 15 - include/linux/platform_data/efm32-uart.h | 19 - include/uapi/linux/serial_core.h | 3 - 30 files changed, 1 insertion(+), 2690 deletions(-) delete mode 100644 arch/arm/boot/dts/efm32gg-dk3750.dts delete mode 100644 arch/arm/boot/dts/efm32gg.dtsi delete mode 100644 arch/arm/configs/efm32_defconfig delete mode 100644 arch/arm/include/debug/efm32.S delete mode 100644 arch/arm/mach-efm32/Makefile delete mode 100644 arch/arm/mach-efm32/Makefile.boot delete mode 100644 arch/arm/mach-efm32/dtmachine.c delete mode 100644 drivers/clk/clk-efm32gg.c delete mode 100644 drivers/clocksource/timer-efm32.c delete mode 100644 drivers/i2c/busses/i2c-efm32.c delete mode 100644 drivers/spi/spi-efm32.c delete mode 100644 drivers/tty/serial/efm32-uart.c delete mode 100644 include/linux/platform_data/efm32-spi.h delete mode 100644 include/linux/platform_data/efm32-uart.h base-commit: 5c8fe583cce542aa0b84adc939ce85293de36e5e -- 2.29.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
2021-01-15spi: Drop unused efm32 bus driverUwe Kleine-König1-1/+0
Support for this machine was just removed, so drop the now unused spi bus driver, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20210114151630.128830-5-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: tegra210-quad: Add support for Tegra210 QSPI controllerSowjanya Komatineni1-0/+1
Tegra SoC has a Quad SPI controller starting from Tegra210. This patch adds support for Tegra210 QSPI controller. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-5-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-05spi: txx9: Remove driverThomas Bogendoerfer1-1/+0
CPU support for TX49xx is getting removed, so remove support SPI driver for it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Link: https://lore.kernel.org/r/20210105140305.141401-5-tsbogend@alpha.franken.de Signed-off-by: Mark Brown <broonie@kernel.org>
2020-10-24Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-1/+0
Pull ARM SoC platform updates from Olof Johansson: "SoC changes, a substantial part of this is cleanup of some of the older platforms that used to have a bunch of board files. In particular: - Remove non-DT i.MX platforms that haven't seen activity in years, it's time to remove them. - A bunch of cleanup and removal of platform data for TI/OMAP platforms, moving over to genpd for power/reset control (yay!) - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them closer to multiplatform support (not quite there yet, but getting close). There are a few other changes too, smaller fixlets, etc. For new platform support, the primary ones are: - New SoC: Hisilicon SD5203, ARM926EJ-S platform. - Cpufreq support for i.MX7ULP" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits) ARM: mstar: Select MStar intc ARM: stm32: Replace HTTP links with HTTPS ones ARM: debug: add UART early console support for SD5203 ARM: hisi: add support for SD5203 SoC ARM: omap3: enable off mode automatically clk: imx: imx35: Remove mx35_clocks_init() clk: imx: imx31: Remove mx31_clocks_init() clk: imx: imx27: Remove mx27_clocks_init() ARM: imx: Remove unused definitions ARM: imx35: Retrieve the IIM base address from devicetree ARM: imx3: Retrieve the AVIC base address from devicetree ARM: imx3: Retrieve the CCM base address from devicetree ARM: imx31: Retrieve the IIM base address from devicetree ARM: imx27: Retrieve the CCM base address from devicetree ARM: imx27: Retrieve the SYSCTRL base address from devicetree ARM: s3c64xx: bring back notes from removed debug-macro.S ARM: s3c24xx: fix Wunused-variable warning on !MMU ARM: samsung: fix PM debug build with DEBUG_LL but !MMU MAINTAINERS: mark linux-samsung-soc list non-moderated ARM: imx: Remove remnant board file support pieces ...
2020-10-09spi: dw: Add Baikal-T1 SPI Controller glue driverSerge Semin1-0/+1
Baikal-T1 is equipped with three DW APB SSI-based MMIO SPI controllers. Two of them are pretty much normal: with IRQ, DMA, FIFOs of 64 words depth, 4x CSs, but the third one as being a part of the Baikal-T1 System Boot Controller has got a very limited resources: no IRQ, no DMA, only a single native chip-select and Tx/Rx FIFO with just 8 words depth available. In order to provide a transparent initial boot code execution the Boot SPI controller is also utilized by an vendor-specific IP-block, which exposes an SPI flash direct mapping interface. Since both direct mapping and SPI controller normal utilization are mutual exclusive only one of these interfaces can be used to access an external SPI slave device. That's why a dedicated mux is embedded into the System Boot Controller. All of that is taken into account in the Baikal-T1-specific DW APB SSI glue driver implemented by means of the DW SPI core module. Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20201007235511.4935-22-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
2020-08-19ARM: s3c24xx: move spi fiq handler into platformArnd Bergmann1-1/+0
The fiq handler needs access to some register definitions that should not be used directly by device drivers. Since this is closely related to the irqchip driver anyway, move it into the same place. Signed-off-by: Arnd Bergmann <arnd@arndb.de> [krzk: Add a header guard in include/linux/spi/s3c24xx-fiq.h, fix SPDX comment style, update maintainer's entry] Co-developed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200806182059.2431-23-krzk%40kernel.org Acked-by: Mark Brown <broonie@kernel.org>
2020-06-19Merge series "mtd: spi-nor: Move cadence-qaudspi to spi-mem framework" from ↵Mark Brown1-0/+1
Vignesh Raghavendra <vigneshr@ti.com>: This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX <vadivel.muruganx.ramuthevar@linux.intel.com> that intended to move cadence-quadspi driver to spi-mem framework Those patches were trying to accomplish too many things in a single set of patches and need to split into smaller patches. This is reduced version of above series. Changes that are intended to make migration easy are split into separate patches. Patches 1 to 3 drop features that cannot be supported under spi-mem at the moment (backward compatibility is maintained). Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to spi-mem and patch 7 moves the driver to drivers/spi folder. I have tested both INDAC mode (used by non TI platforms like Altera SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs. Patches to move move bindings over to "Documentation/devicetree/bindings/spi/" directory and also conversion of bindig doc to YAML will be posted separately. Support for Intel platform would follow that. Resend v3: Rebased onto v5.7-c1 v3: Split handling of probe deferral into separate patch (out of 5/6) Split dropping of redundant WREN to separate patch (out of 5/6) Fix a possible memleak due to lack of spi_master_put() Parse all SPI slave nodes in cqspi_setup_flash() Address misc comments from Tudor on v2 Rebase onto latest spi-nor/next v2: Rework patch 1/6 to keep "cdns,is-decoded-cs" property supported. Ramuthevar Vadivel Murugan (2): mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework spi: Move cadence-quadspi driver to drivers/spi/ Vignesh Raghavendra (6): mtd: spi-nor: cadence-quadspi: Make driver independent of flash geometry mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC mode mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on failure mtd: spi-nor: cadence-quadspi: Fix error path on failure to acquire reset lines mtd: spi-nor: cadence-quadspi: Handle probe deferral while requesting DMA channel mtd: spi-nor: cadence-quadspi: Drop redundant WREN in erase path drivers/mtd/spi-nor/controllers/Kconfig | 11 - drivers/mtd/spi-nor/controllers/Makefile | 1 - drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + .../spi-cadence-quadspi.c} | 541 +++++++----------- 5 files changed, 222 insertions(+), 343 deletions(-) rename drivers/{mtd/spi-nor/controllers/cadence-quadspi.c => spi/spi-cadence-quadspi.c} (74%) base-commit: b3a9e3b9622ae10064826dccb4f7a52bd88c7407 -- 2.26.2 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
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