| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2021-08-25 | powercap: Add Power Limit4 support for Alder Lake SoC | Sumeet Pawnikar | 1 | -0/+2 |
| 2021-03-18 | powercap: Add Hygon Fam18h RAPL support | Pu Wen | 1 | -0/+1 |
| 2020-11-10 | powercap: Add AMD Fam17h RAPL support | Victor Ding | 1 | -1/+19 |
| 2020-11-10 | powercap/intel_rapl_msr: Convert rapl_msr_priv into pointer | Victor Ding | 1 | -15/+18 |
| 2020-10-16 | powercap/intel_rapl: enumerate Psys RAPL domain together with package RAPL do... | Zhang Rui | 1 | -4/+1 |
| 2020-07-27 | powercap: Add Power Limit4 support | Sumeet Pawnikar | 1 | -0/+15 |
| 2019-07-11 | intel_rapl: Fix module autoloading issue | Zhang Rui | 1 | -4/+20 |
| 2019-07-11 | intel_rapl: support two power limits for every RAPL domain | Zhang Rui | 1 | -0/+1 |
| 2019-07-11 | intel_rapl: support 64 bit register | Zhang Rui | 1 | -4/+7 |
| 2019-07-11 | intel_rapl: abstract RAPL common code | Zhang Rui | 1 | -0/+163 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |