starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-07-12	phy: cadence: Sierra: Add single link SGMII register configuration	Marcin Wierzbicki	1	-0/+98
2023-06-09	phy: cadence: sierra: Add a determine_rate hook	Maxime Ripard	1	-0/+1
2023-04-12	phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration	Swapnil Jakhade	1	-2/+139
2023-03-31	phy: cadence: Sierra: Use clk_parent_data to provide parent information	Lars-Peter Clausen	1	-42/+15
2023-03-31	phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`	Lars-Peter Clausen	1	-20/+26
2023-03-20	phy: cadence: phy-cadence-sierra: Convert to platform remove callback returni...	Uwe Kleine-König	1	-4/+2
2022-07-08	phy: cadence: Sierra: Remove unused `regmap` field from state struct	Lars-Peter Clausen	1	-1/+0
2022-04-13	phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configuration	Swapnil Jakhade	1	-3/+190
2022-02-07	phy: cadence: Sierra: Add support for skipping configuration	Aswath Govindraju	1	-25/+57
2022-01-24	phy: cadence: Sierra: fix error handling bugs in probe()	Dan Carpenter	1	-14/+21
2021-12-27	phy: cadence: Sierra: Add support for derived reference clock output	Swapnil Jakhade	1	-1/+108
2021-12-27	phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration	Swapnil Jakhade	1	-1/+376
2021-12-27	phy: cadence: Sierra: Add support for PHY multilink configurations	Swapnil Jakhade	1	-8/+190
2021-12-27	phy: cadence: Sierra: Fix to get correct parent for mux clocks	Swapnil Jakhade	1	-5/+26
2021-12-27	phy: cadence: Sierra: Update single link PCIe register configuration	Swapnil Jakhade	1	-1/+213
2021-12-27	phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation	Swapnil Jakhade	1	-1/+72
2021-12-27	phy: cadence: Sierra: Check cmn_ready assertion during PHY power on	Swapnil Jakhade	1	-0/+45
2021-12-27	phy: cadence: Sierra: Add PHY PCS common register configurations	Swapnil Jakhade	1	-0/+38
2021-12-27	phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ...	Swapnil Jakhade	1	-10/+11
2021-12-27	phy: cadence: Sierra: Add support to get SSC type from device tree	Swapnil Jakhade	1	-1/+5
2021-12-27	phy: cadence: Sierra: Prepare driver to add support for multilink configurations	Swapnil Jakhade	1	-56/+139
2021-12-27	phy: cadence: Sierra: Use of_device_get_match_data() to get driver data	Swapnil Jakhade	1	-9/+4
2021-05-31	phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()	Wang Wensheng	1	-0/+1
2021-03-31	phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocks	Kishon Vijay Abraham I	1	-3/+37
2021-03-31	phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)	Kishon Vijay Abraham I	1	-3/+264
2021-03-31	phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback	Kishon Vijay Abraham I	1	-0/+3
2021-03-31	phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"	Kishon Vijay Abraham I	1	-10/+15
2021-03-31	phy: cadence: Sierra: Explicitly request exclusive reset control	Kishon Vijay Abraham I	1	-2/+2
2021-03-31	phy: cadence: Sierra: Move all reset_control_get*() to a separate function	Kishon Vijay Abraham I	1	-11/+25
2021-03-31	phy: cadence: Sierra: Move all clk_get_*() to a separate function	Kishon Vijay Abraham I	1	-22/+35
2021-03-31	phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes	Kishon Vijay Abraham I	1	-0/+4
2021-03-31	phy: cadence: Sierra: Fix PHY power_on sequence	Kishon Vijay Abraham I	1	-1/+6
2020-11-16	phy: cadence: convert to devm_platform_ioremap_resource	Chunfeng Yun	1	-3/+1
2020-09-16	phy: cadence: Sierra: Constify static structs	Rikard Falkeborn	1	-12/+12
2020-05-18	phy: cadence: sierra: Fix for USB3 U1/U2 state	Sanket Parmar	1	-13/+14
2020-01-14	phy: cadence: Sierra: add phy_reset hook	Roger Quadros	1	-0/+10
2020-01-14	phy: cadence: Sierra: remove redundant initialization of pointer regmap	Colin Ian King	1	-1/+1
2020-01-08	phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()	Kishon Vijay Abraham I	1	-1/+1
2020-01-08	phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to...	Kishon Vijay Abraham I	1	-0/+21
2020-01-08	phy: cadence: Sierra: Change MAX_LANES of Sierra to 16	Kishon Vijay Abraham I	1	-1/+21
2020-01-08	phy: cadence: Sierra: Check for PLL lock during PHY power on	Kishon Vijay Abraham I	1	-1/+32
2020-01-08	phy: cadence: Sierra: Get reset control "array" for each link	Kishon Vijay Abraham I	1	-1/+1
2020-01-08	phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ex...	Anil Varughese	1	-96/+254
2020-01-08	phy: cadence: Sierra: Modify register macro names to be in sync with Sierra u...	Kishon Vijay Abraham I	1	-83/+84
2020-01-08	phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops	Kishon Vijay Abraham I	1	-6/+9
2020-01-08	phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC	Kishon Vijay Abraham I	1	-0/+14
2020-01-08	phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers	Kishon Vijay Abraham I	1	-54/+237
2020-01-08	phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources	Kishon Vijay Abraham I	1	-2/+2
2018-12-12	phy: cadence: Add driver for Sierra PHY	Alan Douglas	1	-0/+395