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path: root/drivers/gpu/drm
AgeCommit message (Expand)AuthorFilesLines
2020-05-22drm/i915/gem: Avoid iterating an empty listChris Wilson1-6/+9
2020-05-22drm/i915: Fix includes and local vars orderStanislav Lisovskiy6-24/+30
2020-05-22drm/i915/ehl: Extend w/a 14010685332 to JSP/MCCSwathi Dhanavanthri1-2/+4
2020-05-22drm/i915: Remove unneeded hack now for CDCLKStanislav Lisovskiy1-12/+0
2020-05-22drm/i915: Adjust CDCLK accordingly to our DBuf bw needsStanislav Lisovskiy8-15/+220
2020-05-22drm/i915: Introduce for_each_dbuf_slice_in_mask macroStanislav Lisovskiy2-0/+8
2020-05-22drm/i915: Plane configuration affects CDCLK in Gen11+Stanislav Lisovskiy1-1/+1
2020-05-22drm/i915: Check plane configuration properlyStanislav Lisovskiy1-1/+7
2020-05-22drm/i915: Extract cdclk requirements checking to separate functionStanislav Lisovskiy1-8/+22
2020-05-22drm/i915: Decouple cdclk calculation from modeset checksStanislav Lisovskiy1-10/+12
2020-05-21drm/i915: Remove PIN_UPDATE for i915_vma_pinChris Wilson3-149/+3
2020-05-21drm/i915: Avoid using rq->engine after free during i915_fence_releaseChris Wilson1-2/+33
2020-05-21drm/i915: Disable semaphore inter-engine sync without timeslicingChris Wilson1-2/+2
2020-05-21drm/i915/selftests: Flush the submission, not cancel it!Chris Wilson1-1/+1
2020-05-21drm/i915/selftests: Measure CS_TIMESTAMPChris Wilson1-0/+132
2020-05-20drm/i915/ehl: Wa_22010271021Matt Atwood1-0/+6
2020-05-20drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and BMatt Roper1-13/+17
2020-05-20drm/i915/rkl: Add power well supportMatt Roper2-3/+186
2020-05-20drm/i915/rkl: Limit number of universal planes to 5Matt Roper6-13/+35
2020-05-20drm/i915/rkl: Update memory bandwidth parametersMatt Roper1-1/+9
2020-05-20drm/i915/gt: Remove errant assertion in __intel_context_do_pinChris Wilson1-2/+0
2020-05-20drm/i915/rkl: Add PCH supportMatt Roper1-3/+5
2020-05-20drm/i915/rkl: Load DMC firmware for Rocket LakeMatt Roper1-1/+9
2020-05-20drm/i915/rkl: Re-use TGL GuC/HuC firmwareMatt Roper1-0/+3
2020-05-20drm/i915/rkl: Add RKL platform info and PCI idsMatt Roper4-0/+20
2020-05-19drm/i915/gt: Incorporate the virtual engine into timeslicingChris Wilson1-6/+24
2020-05-19drm/i915/gt: Kick virtual siblings on timeslice outChris Wilson1-1/+1
2020-05-19drm/i915/selftests: Add tests for timeslicing virtual enginesChris Wilson1-3/+197
2020-05-19drm/i915/selftests: Check for an initial-breadcrumb in wait_for_submit()Chris Wilson1-1/+1
2020-05-19drm/i915/selftests: Restore to default heartbeatChris Wilson4-109/+67
2020-05-19drm/i915/selftests: Change priority overflow detectionChris Wilson1-3/+3
2020-05-19drm/i915: Don't set queue-priority hint when supressing the rescheduleChris Wilson1-8/+8
2020-05-19drm/i915/selftests: Measure dispatch latencyChris Wilson1-0/+823
2020-05-19drm/i915/runtime_pm: Prefer drm_WARN* over WARN*Pankaj Bharadiya1-11/+28
2020-05-19drm/i915/pm: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya1-25/+38
2020-05-19drm/i915/pmu: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya1-3/+9
2020-05-19drm/i915/i915_drv: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya1-1/+2
2020-05-19drm/i915/gem: Prefer drm_WARN* over WARN*Pankaj Bharadiya3-3/+4
2020-05-19drm/i915/display/tc: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya1-5/+9
2020-05-19drm/i915/display/sdvo: Prefer drm_WARN* over WARN*Pankaj Bharadiya1-7/+14
2020-05-19drm/i915/display/dp: Prefer drm_WARN* over WARN*Pankaj Bharadiya1-9/+15
2020-05-19drm/i915/display/display_power: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya1-11/+24
2020-05-19drm/i915: Fix AUX power domain toggling across TypeC mode resetsImre Deak1-2/+3
2020-05-19drm/i915: Read out hrawclk on all gen3+ platformsVille Syrjälä2-25/+42
2020-05-19drm/i915: Document our lackluster FSB frequency readoutVille Syrjälä1-1/+10
2020-05-19drm/i915: Fix 400 MHz FSB readout on elkVille Syrjälä2-7/+8
2020-05-18drm/i915/display: Return error from dbuf allocation failureChris Wilson1-1/+1
2020-05-18drm/i915: Fix dbuf slice mask when turning off all the pipesVille Syrjälä1-0/+24
2020-05-18drm/i915/gt: Reuse the tasklet priority for virtual as their siblingsChris Wilson1-2/+2
2020-05-18drm/i915/selftests: Refactor sibling selectionChris Wilson1-41/+27
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