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path: root/drivers/gpu/drm
AgeCommit message (Expand)AuthorFilesLines
2022-02-23drm/i915: Extract intel_bw_check_data_rate()Ville Syrjälä1-21/+34
2022-02-23drm/i915: Extract icl_qgv_points_mask()Ville Syrjälä1-13/+22
2022-02-23drm/i915: Properly clear crtc state when disabling it fully, againVille Syrjälä1-3/+5
2022-02-23drm/i915: Remove odd any_ms=true assignmentVille Syrjälä1-3/+1
2022-02-23drm/i915: Dump hw.enable and pipe_modeVille Syrjälä1-2/+5
2022-02-23drm/i915: Dump the crtc hw state alwaysVille Syrjälä1-9/+7
2022-02-23Revert "drm/i915/display/vrr: Reset VRR capable property on a long hpd"Ville Syrjälä1-13/+4
2022-02-23drm/i915/adl-n: Add PCH Support for Alder Lake NTejas Upadhyay2-0/+2
2022-02-22drm/i915/display/vrr: Reset VRR capable property on a long hpdManasi Navare1-4/+13
2022-02-21drm/i915/adlp: Add TypeC PHY TBT->DP-alt/legacy mode switch workaroundImre Deak2-1/+24
2022-02-21drm/i915/pxp: prefer forward declaration over includesJani Nikula1-1/+1
2022-02-21drm/i915/reg: split out icl_dsi_regs.hJani Nikula4-333/+344
2022-02-21drm/i915/reg: split out vlv_dsi_regs.h and vlv_dsi_pll_regs.hJani Nikula8-575/+595
2022-02-21drm/i915/dsi: add separate init timer mask definition for ICL DSIJani Nikula2-1/+2
2022-02-21drm/i915/dsi: disassociate VBT video transfer mode from register valuesJani Nikula4-19/+39
2022-02-20iosys-map: Add offset to iosys_map_memcpy_to()Lucas De Marchi2-2/+2
2022-02-19drm/i915/dg2: Enable 5th portMatt Roper4-3/+20
2022-02-19drm/i915/dg2: Drop 38.4 MHz MPLLB tablesMatt Roper1-207/+1
2022-02-19drm/i915: Fix for PHY_MISC_TC1 offsetJouni Högander2-3/+5
2022-02-18drm/i915: Pimp icl+ sagv pre/post updateVille Syrjälä1-18/+17
2022-02-18drm/i915: Split pre-icl vs. icl+ SAGV hooks apartVille Syrjälä1-40/+74
2022-02-18drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGVVille Syrjälä1-2/+16
2022-02-18drm/i915: Correctly populate use_sagv_wm for all pipesVille Syrjälä1-11/+11
2022-02-18drm/i915: Drop pointless i830 PIPECONF readVille Syrjälä1-4/+2
2022-02-18drm/i915: Make the CHV CGM CSC register writes locklessVille Syrjälä1-10/+10
2022-02-18drm/i915: Make the pipe/output CSC register writes locklessVille Syrjälä1-40/+40
2022-02-18drm/i915: Move PIPE_CHICKEN RMW out from the vblank evade critical sectionVille Syrjälä1-3/+5
2022-02-18drm/i915/display: Implement Wa_16013835468José Roberto de Souza2-7/+46
2022-02-18drm/i915/display: Group PSR2 prog sequences and workaroundsJosé Roberto de Souza1-40/+37
2022-02-18drm/i915/display/tgl+: Implement new PLL programming stepJosé Roberto de Souza8-13/+65
2022-02-18drm/i915: Disconnect PHYs left connected by BIOS on disabled portsImre Deak1-6/+20
2022-02-18drm/i915/dp: remove accidental static on what should be a local variableJani Nikula1-1/+1
2022-02-18drm/i915: Polish ilk+ wm register bitsVille Syrjälä3-51/+49
2022-02-18drm/i915: Introduce intel_crtc_planes_update_arm()Ville Syrjälä3-18/+23
2022-02-18drm/i915: Clean up SSKPD/MLTR definesVille Syrjälä3-26/+25
2022-02-18drm/i915/dg2: Print PHY name properly on calibration errorMatt Roper1-1/+1
2022-02-17drm/i915/lrc: replace include with forward declarationsJani Nikula2-2/+5
2022-02-17drm/i915/lrc: move lrc_get_runtime() to intel_lrc.cJani Nikula4-11/+13
2022-02-17drm/i915/fbdev: hide struct intel_fbdev in intel_fbdev.cJani Nikula2-21/+17
2022-02-17drm/i915/fbdev: add intel_fbdev_framebuffer() helperJani Nikula3-3/+18
2022-02-17drm/i915: fix build issue when using clangTong Zhang1-0/+1
2022-02-17drm/i915/gvt: #include drm_edid.h for drm_edid_block_valid()Jani Nikula1-0/+2
2022-02-16drm/i915: Add missing intel_mchbar_regs.hMatt Roper1-0/+221
2022-02-16drm/i915: Move MCHBAR registers to their own headerMatt Roper16-210/+14
2022-02-16drm/i915: Define MCH registers relative to MCHBAR_MIRROR_BASEMatt Roper1-6/+6
2022-02-16drm/i915/gt: Order GT registers by MMIO offsetMatt Roper1-1059/+1064
2022-02-16drm/i915/gt: Use consistent offset notation in intel_gt_regs.hMatt Roper1-103/+103
2022-02-16drm/i915/gt: Cleanup spacing of intel_gt_regs.hMatt Roper1-1069/+1069
2022-02-16drm/i915/gt: Use parameterized RING_MI_MODEMatt Roper4-12/+10
2022-02-16drm/i915/gt: Move SFC lock bits to intel_engine_regs.hMatt Roper3-26/+24
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-02 20:37:52 +0300