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path: root/drivers/gpu/drm/xe/regs/xe_engine_regs.h
AgeCommit message (Expand)AuthorFilesLines
2023-12-27drm/xe/xe2: Add workaround 16020183090Lucas De Marchi1-0/+4
2023-12-22drm/xe: Define registers used by memory based irq processingMichal Wajdeczko1-0/+2
2023-12-21drm/xe: Move engine base offsets to engine register headerMatt Roper1-0/+33
2023-12-21drm/xe: Fix whitespace in register definitionsMatt Roper1-2/+2
2023-12-21drm/xe: Move some per-engine register definitions to the engine headerMatt Roper1-0/+21
2023-12-21drm/xe: Drop "_REG" suffix from CSFE_CHICKEN1Matt Roper1-5/+4
2023-12-21drm/xe: Remove duplicate RING_MAX_NONPRIV_SLOTS definitionMatt Roper1-1/+0
2023-12-21drm/xe/xe2: Add workaround 18032095049 and 16021639441Tejas Upadhyay1-0/+5
2023-12-21drm/xe/xe2: Add workaround 14019449301Tejas Upadhyay1-0/+3
2023-12-21drm/xe/xelpmp: Add Wa_16021867713Gustavo Sousa1-0/+3
2023-12-21drm/xe: Remove devcoredump readout of IPEIRJosé Roberto de Souza1-2/+0
2023-12-21drm/xe: Fix devcoredump readout of IPEHRJosé Roberto de Souza1-1/+0
2023-12-21drm/xe/pvc: Force even num engines to use 64BNiranjana Vishwanathapura1-0/+1
2023-12-21drm/xe/pvc: Blacklist BCS_SWCTRL registerNiranjana Vishwanathapura1-0/+2
2023-12-21drm/xe: enable idle msg and set hysteresis for GSCCSDaniele Ceraolo Spurio1-0/+4
2023-12-20drm/xe: Set default MOCS value for copy cs instructionsJosé Roberto de Souza1-0/+6
2023-12-20drm/xe: Set default MOCS value for cs instructionsJosé Roberto de Souza1-0/+12
2023-12-20drm/xe: Annotate masked registers used by RTPLucas De Marchi1-1/+1
2023-12-20drm/xe: Use XE_REG/XE_REG_MCRLucas De Marchi1-37/+37
2023-12-20drm/xe: Use REG_FIELD/REG_BIT for all regs/*.hLucas De Marchi1-12/+12
2023-12-20drm/xe: Drop gen afixes from registersLucas De Marchi1-4/+4
2023-12-20drm/xe: Fix print of RING_EXECLIST_SQ_CONTENTS_HIRodrigo Vivi1-1/+2
2023-12-20drm/xe: Do not spread i915_reg_defs.h includeLucas De Marchi1-1/+1
2023-12-20drm/xe: Remove dependency on intel_engine_regs.hLucas De Marchi1-0/+98
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