| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-11-09 | drm/nouveau/fifo: add chid_nr() | Ben Skeggs | 1 | -45/+0 | |
| - reads channel count from GPU from gm200 onwards - removes gm20b/gp10b (they become identical to gm200/gp100) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> | |||||
| 2021-02-11 | drm/nouveau/fifo: switch to instanced constructor | Ben Skeggs | 1 | -2/+3 | |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> | |||||
| 2019-08-23 | drm/nouveau/fifo/gk104-: fix parsing of mmu fault data | Ben Skeggs | 1 | -0/+1 | |
| Pascal was particularly incorrect, as the register changed to be more in the same format as the MMU fault buffers are. Shouldn't have impacted much more than confusing MMU fault log messages. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2018-12-11 | drm/nouveau/fifo/gm200-: read pbdma count more directly | Ben Skeggs | 1 | -1/+1 | |
| The trick we used (and still use for older GPUs) doesn't work on Turing. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2018-12-11 | drm/nouveau/fifo/gk104-: group pbdma functions together | Ben Skeggs | 1 | -1/+1 | |
| We're about to be adding more of them. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2018-05-18 | drm/nouveau/fifo/gm107-: write instance address in channel runlist entry | Ben Skeggs | 1 | -1/+1 | |
| RM does this for some reason. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2018-05-18 | drm/nouveau/fifo/gk208-: write pbdma timeout regs during initialisation | Ben Skeggs | 1 | -0/+1 | |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2018-05-18 | drm/nouveau/fifo/gk110-: support writing channel group runlist entries | Ben Skeggs | 1 | -1/+1 | |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2018-05-18 | drm/nouveau/fifo/gk104-: add interfaces to support different runlist layouts | Ben Skeggs | 1 | -0/+1 | |
| This will be required to support features on newer hardware. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2018-05-18 | drm/nouveau/fifo/gk104-: simplify definition of channel classes | Ben Skeggs | 1 | -4/+3 | |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2018-05-18 | drm/nouveau/fifo/gk104-: allow fault recovery code to be called by other subdevs | Ben Skeggs | 1 | -0/+1 | |
| This will be required to support Volta. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2016-05-20 | drm/nouveau/fifo/gm107-: remove engines from mmu engine mapping array | Ben Skeggs | 1 | -1/+1 | |
| These are specified by PTOP on Maxwell GPUs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2016-05-20 | drm/nouveau/fifo/gk104-: abstract mmu fault data structures | Ben Skeggs | 1 | -0/+4 | |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2016-05-20 | drm/nouveau/fifo/gk104-: subclass func | Ben Skeggs | 1 | -8/+1 | |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2016-03-14 | drm/nouveau: s/gm204/gm200/ in a number of places | Ben Skeggs | 1 | -1/+1 | |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2015-08-28 | drm/nouveau/fifo: convert to new-style nvkm_engine | Ben Skeggs | 1 | -10/+20 | |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
| 2015-08-28 | drm/nouveau/fifo: add GM20B fifo | Alexandre Courbot | 1 | -0/+34 | |
| GM20B has a 512-channels FIFO similar to GK104. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
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