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path: root/drivers/gpu/drm/i915/intel_dsi_pll.c
AgeCommit message (Expand)AuthorFilesLines
2015-12-10drm/i915: Separate cherryview from valleyviewWayne Boyer1-3/+3
2015-10-06drm/i915/bxt: vlv_dsi_reset_clocks() can be statickbuild test robot1-2/+2
2015-10-02drm/i915/bxt: get DSI pixelclockShashank Sharma1-0/+35
2015-10-02drm/i915/bxt: DSI disable and post-disableShashank Sharma1-0/+39
2015-10-02drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma1-0/+42
2015-09-23drm/i915/bxt: Disable DSI PLL for BXTShashank Sharma1-1/+31
2015-09-23drm/i915/bxt: Enable BXT DSI PLLShashank Sharma1-1/+94
2015-07-03drm/i915: Changes required to enable DSI Video Mode on CHTGaurav K Singh1-6/+20
2015-07-03drm/i915: Support for higher DSI clkGaurav K Singh1-2/+2
2015-07-03drm/i915/dsi: abstract dsi bpp derivation from pixel formatJani Nikula1-43/+24
2015-05-28drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä1-7/+7
2015-05-20drm/i915/dsi: add support for DSI PLL N1 divisor valuesJani Nikula1-6/+11
2015-05-20drm/i915: clean up dsi pll calculationJani Nikula1-36/+17
2014-12-10drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port CGaurav K Singh1-2/+3
2014-12-05drm/i915: cck reg used for checking DSI Pll lockedGaurav K Singh1-2/+4
2014-12-05drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual linkGaurav K Singh1-0/+3
2014-08-08drm/i915: Align intel_dsi*.c files a bitDaniel Vetter1-4/+4
2014-08-08drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar1-6/+3
2014-08-07drm/i915: Add correct hw/sw config check for DSI encoderShobhit Kumar1-0/+81
2013-12-12drm/i915: Try harder to get best m, n, p values with minimal errorShobhit Kumar1-10/+20
2013-12-12drm/i915: Compute dsi_clk from pixel clockShobhit Kumar1-58/+31
2013-09-17drm/i915: Use adjusted_mode in DSI PLL calculationsVille Syrjälä1-2/+2
2013-09-04drm/i915: add VLV DSI PLL Calculationsymohanma1-0/+317
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