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path: root/drivers/gpu/drm/i915/intel_dpio_phy.c
AgeCommit message (Expand)AuthorFilesLines
2018-04-10drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeoutImre Deak1-5/+6
2018-02-19drm: intel_dpio_phy: fix kernel-doc comments at nested structMauro Carvalho Chehab1-1/+1
2017-11-09drm/i915: Nuke intel_digital_port->portVille Syrjälä1-7/+5
2017-11-09drm/i915: Pass crtc state to DPIO PHY functionsVille Syrjälä1-44/+43
2017-11-07drm/i915: Simplify onion for bxt_ddi_phy_init()Chris Wilson1-10/+10
2017-10-27drm/i915: Fix BXT lane latency optimal setting with MSTVille Syrjälä1-2/+1
2017-10-03drm/i915: Fix DDI PHY init if it was already onImre Deak1-20/+0
2016-12-02drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.Rodrigo Vivi1-12/+3
2016-12-02drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira1-15/+99
2016-12-02drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira1-1/+0
2016-11-02drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequenceAnder Conselvan de Oliveira1-21/+0
2016-10-28drm/i915: Address broxton phy registers based on phy and channel numberAnder Conselvan de Oliveira1-14/+54
2016-10-28drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_infoAnder Conselvan de Oliveira1-17/+55
2016-10-28drm/i915: Create a struct to hold information about the broxton physAnder Conselvan de Oliveira1-10/+55
2016-10-28drm/i915: Move broxton vswing sequence to intel_dpio_phy.cAnder Conselvan de Oliveira1-0/+39
2016-10-28drm/i915: Move DPIO phy documentation section to intel_dpio_phy.cAnder Conselvan de Oliveira1-0/+91
2016-10-28drm/i915: Move broxton phy code to intel_dpio_phy.cAnder Conselvan de Oliveira1-0/+327
2016-07-04drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson1-5/+5
2016-04-29drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.cAnder Conselvan de Oliveira1-0/+15
2016-04-29drm/i915: Unduplicate pre encoder enabling phy codeAnder Conselvan de Oliveira1-0/+30
2016-04-29drm/i915: Unduplicate VLV phy pre pll enabling codeAnder Conselvan de Oliveira1-0/+28
2016-04-29drm/i915: Unduplicate VLV signal level codeAnder Conselvan de Oliveira1-0/+26
2016-04-29drm/i915: Unduplicate CHV encoders' post pll disable codeAnder Conselvan de Oliveira1-0/+33
2016-04-29drm/i915: Unduplicate CHV pre-encoder enabling phy logicAnder Conselvan de Oliveira1-0/+92
2016-04-29drm/i915: Unduplicate CHV phy-releated pre pll enabling codeAnder Conselvan de Oliveira1-0/+81
2016-04-29drm/i915: Unduplicate chv_data_lane_soft_reset()Ander Conselvan de Oliveira1-0/+43
2016-04-29drm/i915: Unduplicate CHV signal level codeAnder Conselvan de Oliveira1-0/+122
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