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path: root/drivers/gpu/drm/i915/intel_bios.c
AgeCommit message (Expand)AuthorFilesLines
2011-10-21drm/i915: Remove "i2c_speed" nonsense from child device tableAdam Jackson1-4/+2
2011-10-21Merge branch 'fix-pch-refclk' into fooKeith Packard1-3/+10
2011-09-27drv/i915: Pull display_clock_mode out of VBT tableKeith Packard1-2/+4
2011-09-27drm/i915: Use DRM_DEBUG_KMS for all messages in intel_bios.cKeith Packard1-2/+7
2011-09-27drm/i915: broken copyright encoding in intel_bios.cKeith Packard1-1/+1
2011-09-20Drivers: i915: Fix all space related issues.Akshay Joshi1-2/+2
2011-07-14drm/i915/bios: Avoid temporary allocation whilst searching for downclockChris Wilson1-59/+83
2011-04-28drm: Verify debug message argumentsJoe Perches1-3/+3
2011-02-22Revert "drm/i915: Disable SSC for outputs other than LVDS or DP"Chris Wilson1-1/+0
2011-02-01drm/i915: Override SDVO panel type in VBTChris Wilson1-8/+14
2011-01-19drm/i915: Disable SSC for outputs other than LVDS or DPChris Wilson1-0/+1
2011-01-19drm/i915/bios: Change default clock source on PineView to use SSCBryan Freed1-8/+23
2011-01-13drm/i915: Add a module option to override the use of SSCChris Wilson1-11/+6
2010-12-30Revert "drm/i915/bios: Reverse order of 100/120 Mhz SSC clocks"Chris Wilson1-1/+1
2010-12-15drm/i915/bios: Reverse order of 100/120 Mhz SSC clocksChris Wilson1-1/+1
2010-10-21drm/i915: IS_IRONLAKE is synonymous with gen == 5Chris Wilson1-2/+2
2010-10-19drm/i915: Initialize panel timing registers if VBIOS did notBryan Freed1-2/+19
2010-10-08drm/i915: fetch eDP configuration data from the VBTJesse Barnes1-11/+49
2010-09-30i915: Added function to initialize VBT settingsSimon Que1-13/+23
2010-09-28drm/i915/sdvo: Fix GMBUSificationChris Wilson1-0/+9
2010-09-24drm/i915: Parse the eDP link configuration from the vBIOSChris Wilson1-14/+27
2010-09-22drm/i915: Don't offset the pin used for crt_ddcChris Wilson1-1/+1
2010-09-18drm/i915: use GMBUS to manage i2c linksChris Wilson1-12/+4
2010-09-12drm/i915/bios: Prevent NULL dereference after allocation failureChris Wilson1-0/+2
2010-09-08drm/i915: Use the VBT from OpRegion when available (v3)Chris Wilson1-31/+42
2010-06-01drm/i915: Honor sync polarity from VBT panel timing descriptorsAdam Jackson1-0/+10
2010-05-11drm/i915: Fix DDC bus selection for multifunction SDVOAdam Jackson1-0/+1
2010-03-17drivers/gpu/drm/i915/intel_bios.c: fix continuation line formatsJoe Perches1-2/+3
2010-02-27drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.Eric Anholt1-1/+2
2010-01-16drm/i915: parse eDP panel color depth from VBT blockZhenyu Wang1-0/+32
2010-01-16drm/i915: disable LVDS downclock by defaultJesse Barnes1-1/+2
2009-12-08drm/i915: Fix product names and #definesAdam Jackson1-1/+1
2009-12-01drm/i915: parse child device from VBTZhao Yakui1-0/+65
2009-12-01drm/i915: fix gpio register detection logic for BIOS without VBTShaohua Li1-4/+0
2009-11-26drm/i915: Check whether the LVDS downclock is found in VBTZhao Yakui1-0/+42
2009-11-06drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMSZhao Yakui1-12/+12
2009-10-13drm/i915: Fix render reclock availability detection.Andy Lutomirski1-8/+6
2009-09-18drm/i915: Fix SSC frequence for IGDNGZhenyu Wang1-0/+3
2009-09-05drm/i915: add dynamic clock frequency controlJesse Barnes1-1/+7
2009-08-30drm/i915: Improve CRTDDC mapping by using VBT infoDavid Müller (ELSOFT AG)1-3/+48
2009-07-30drm/i915: Add eDP support on IGDNG mobile chipZhenyu Wang1-0/+21
2009-07-30drm/I915: Fix offset to DVO timings in LVDS dataZhao Yakui1-9/+10
2009-07-11drm/i915: Fix for LVDS VBT change on IGDNGZhenyu Wang1-1/+9
2009-07-01drm/i915: Set SSC frequency for 8xx chips correctlyling.ma@intel.com1-4/+6
2009-06-23drm/i915: fix LFP data fetchJesse Barnes1-1/+11
2009-06-19drm: Remove memory debugging infrastructure.Eric Anholt1-4/+2
2009-06-05drm/i915: parse VBT general definition block to get the SDVO device infoyakui_zhao1-1/+85
2009-05-22drm/i915: Fetch SDVO LVDS mode lines from VBT, then reserve themMa Ling1-30/+72
2009-02-25drm/i915: handle bogus VBT panel timingJesse Barnes1-0/+6
2009-02-20drm: Use spread spectrum when the bios tells us it's ok.Kristian Høgsberg1-0/+8
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