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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2014-06-05drm/i915: Enable interrupt-based AGPBUSY# enable on 85xVille Syrjälä1-0/+4
2014-06-05drm/i915: Flip the sense of AGPBUSY_DIS bitVille Syrjälä1-1/+1
2014-05-22drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elkVille Syrjälä1-0/+4
2014-05-22drm/i915: Add a brief description of the VLV display PHY internalsVille Syrjälä1-4/+81
2014-05-21drm/i915: Fix mmio vs. CS flip race on ILK+Ville Syrjälä1-0/+1
2014-05-20drm/i915: Drop /** */ comments from i915_reg.hVille Syrjälä1-123/+123
2014-05-20drm/i915/chv: Add a bunch of pre production workaroundsVille Syrjälä1-0/+3
2014-05-20drm/i915/chv: Use RMW to toggle swing calc initVille Syrjälä1-0/+7
2014-05-20drm/i915/chv: Don't do group access reads from TX lanes eitherVille Syrjälä1-0/+11
2014-05-20drm/i915/chv: Don't use PCS group access readsVille Syrjälä1-0/+14
2014-05-20drm/i915/chv: Set soft reset override bit for data lane resetsVille Syrjälä1-0/+1
2014-05-20drm/i915/chv: Register port D encoders and connectorsVille Syrjälä1-0/+1
2014-05-20drm/i915/chv: Fix PORT_TO_PIPE for CHVVille Syrjälä1-0/+2
2014-05-20drm/i915/chv: Add cursor pipe offsetsVille Syrjälä1-12/+18
2014-05-20drm/i915/chv: Fix gmbus for port DVille Syrjälä1-0/+1
2014-05-20drm/i915/chv: Add CHV display supportRafael Barbalho1-3/+8
2014-05-20drm/i915: Fix ILK GPU reset domain bitsVille Syrjälä1-1/+7
2014-05-19drm/i915: Add MIPI mmio reg baseShashank Sharma1-0/+1
2014-05-19drm/i915: rename IOSF sideband opcodes according to the specImre Deak1-5/+0
2014-05-16drm/i915: Enable PM Interrupts target via Display Interface.Deepak S1-0/+1
2014-05-16drm/i915/bdw: Implement a basic PM interrupt handlerBen Widawsky1-0/+1
2014-05-12drm/i915/chv: Pipe select change for DP and HDMIChon Ming Lee1-0/+6
2014-05-12drm/i915/chv: Add update and enable pll for CherryviewChon Ming Lee1-0/+70
2014-05-12drm/i915/chv: Trigger phy common lane resetChon Ming Lee1-0/+8
2014-05-12drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2Chon Ming Lee1-0/+6
2014-05-12drm/i915/chv: Add DPIO offset for Cherryview. v3Chon Ming Lee1-0/+1
2014-05-12drm/i915/chv: Add DDL register defines for CherryviewVille Syrjälä1-0/+29
2014-05-07drm/i915: add various missing GTI/Gunit register definitionsImre Deak1-1/+40
2014-05-06drm/i915/chv: Add DPINVGTT registers defines for CherryviewVille Syrjälä1-1/+11
2014-05-06drm/i915/chv: Add display interrupt registers bits for CherryviewVille Syrjälä1-1/+20
2014-05-06drm/i915/chv: Add DPFLIPSTAT register bits for CherryviewVille Syrjälä1-0/+7
2014-05-06drm/i915/chv: Add PIPESTAT register bits for CherryviewVille Syrjälä1-0/+8
2014-05-05drm/i915: vlv: add RC6 residency countersImre Deak1-0/+3
2014-05-05drm/i915: vlv: clean up GTLC wake control/status register macrosImre Deak1-2/+8
2014-05-05drm/i915:Initialize the second BSD ring on BDW GT3 machineZhao Yakui1-0/+1
2014-04-10drm/i915: Add support for DRRS to switch RRPradeep Bhat1-0/+1
2014-04-09drm/i915: Add more registers to the whitelist for mesaBrad Volkin1-0/+9
2014-04-09drm/i915: Rename GEN8_PIPE_FLIP_DONE to PRIMARY_FLIP_DONEDamien Lespiau1-1/+1
2014-04-09drm/i915/bdw: Provide a gen8 version of SRMDamien Lespiau1-0/+1
2014-04-09drm/i915: Protect the argument expansion in LRI and SRM macrosDamien Lespiau1-2/+2
2014-04-09drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush'Akash Goel1-0/+1
2014-04-03drm/i915: Move all ring resets before setting the HWS pageChris Wilson1-0/+1
2014-04-03drm/i915: Fix framecount offsetRafael Barbalho1-3/+3
2014-04-02drm/i915/bdw: Expand FADD to 64bitBen Widawsky1-0/+1
2014-04-02drm/i915: Add OACONTROL to the command parser register whitelist.Kenneth Graunke1-0/+2
2014-04-02drm/i915: Reject commands that would store to global HWS pageBrad Volkin1-0/+1
2014-04-02drm/i915: Enable PPGTT command parser checksBrad Volkin1-0/+6
2014-04-02drm/i915: Reject commands that explicitly generate interruptsBrad Volkin1-0/+1
2014-04-02drm/i915: Enable register whitelist checksBrad Volkin1-0/+3
2014-04-02drm/i915: Add register whitelist for DRM masterBrad Volkin1-0/+6
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