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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2024-08-29drm/i915/dsb: Hook up DSB error interruptsVille Syrjälä1-0/+4
2024-08-12drm/i915/bmg: Read display register timeoutMitul Golani1-0/+2
2024-06-19drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtlVille Syrjälä1-0/+2
2024-06-19drm/i915: Enable pipeDMC fault interrupts on tgl+Ville Syrjälä1-0/+2
2024-06-19drm/i915: Nuke the intermediate pipe fault bitmasksVille Syrjälä1-18/+0
2024-06-19drm/i915: Extend GEN9_PIPE_PLANE_FLIP_DONE() to cover all universal planesVille Syrjälä1-1/+5
2024-06-19drm/i915: Sort bdw+ pipe interrupt bitsVille Syrjälä1-11/+11
2024-06-19drm/i915: Document bdw+ pipe interrupt bitsVille Syrjälä1-21/+21
2024-06-19drm/i915: Use REG_BIT() for bdw+ pipe interruptsVille Syrjälä1-27/+27
2024-06-14drm/i915: remove unused pipe/plane B register macrosJani Nikula1-21/+0
2024-06-14drm/i915: relocate some DSPCNTR reg bit definitionsJani Nikula1-2/+0
2024-06-11drm/i915: Separate VRR related register definitionsMitul Golani1-100/+0
2024-06-11drm/i915: Update indentation for VRR registers and bitsMitul Golani1-87/+87
2024-06-07drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANSJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCYJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_MSA_MISCJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUSJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N1Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M1Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_M2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N1Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_M1Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to SWF3Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to SWF1Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to SWF0Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to CHV_CANVASJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to CHV_BLENDJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_FLIPCOUNT_G4XJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4XJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to DSPFW3Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to DSPFW2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to DSPFW1Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to DSPARBJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to ICL_PIPESTATUSJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_ARB_CTLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPESTATJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPEFRAMEPIXELJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPEFRAMEJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPEDSLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANSCONFJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PFIT_AUTO_RATIOSJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOSJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PFIT_CONTROLJani Nikula1-1/+1
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-26 10:49:47 +0300