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path: root/drivers/gpu/drm/i915/gt/intel_ring_submission.c
AgeCommit message (Expand)AuthorFilesLines
2020-07-09drm/i915: Release shortlived maps of longlived objectsChris Wilson1-1/+1
2020-07-08drm/i915: Move the engine mask to intel_gt_infoDaniele Ceraolo Spurio1-1/+1
2020-06-03drm/i915: Drop i915_request.i915 backpointerChris Wilson1-3/+3
2020-06-02drm/i915/gt: Move legacy context wa to intel_workaroundsChris Wilson1-28/+0
2020-06-02drm/i915/gt: Split low level gen2-7 CS emittersChris Wilson1-805/+27
2020-04-29drm/i915/gt: Keep a no-frills swappable copy of the default context stateChris Wilson1-12/+4
2020-03-19drm/i915/ring_submission: use drm_device based logging macros.Wambui Karuga1-15/+18
2020-03-15drm/i915/gt: Restrict gen7 w/a batch to HaswellChris Wilson1-1/+1
2020-03-07drm/i915/gt: Wait for the wa batch to be pinnedChris Wilson1-0/+4
2020-03-06drm/i915/gen7: Clear all EU/L3 residual contextsPrathap Kumar Valsan1-1/+2
2020-03-06drm/i915: Add mechanism to submit a context WA on ring submissionMika Kuoppala1-4/+134
2020-03-04drm/i915: Apply i915_request_skip() on submissionChris Wilson1-3/+1
2020-02-27drm/i915: significantly reduce the use of <drm/i915_drm.h>Jani Nikula1-2/+0
2020-02-07drm/i915/gt: Set the PP_DIR registers upon enabling ring submissionChris Wilson1-14/+26
2020-02-01drm/i915: Move ringbuffer WAs to engine workaround listDaniele Ceraolo Spurio1-37/+0
2020-01-30drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.cWambui Karuga1-1/+2
2020-01-22drm/i915/gt: Make WARN* drm specific where drm_priv ptr is availablePankaj Bharadiya1-3/+4
2020-01-09drm/i915/gt: Pull context activation into central intel_context_pin()Chris Wilson1-15/+1
2020-01-07drm/i915/gtt: split up i915_gem_gttMatthew Auld1-0/+1
2020-01-07drm/i915/gt: Take responsibility for engine->release as the last stepChris Wilson1-2/+3
2020-01-03drm/i915/gt: Ignore stale context state upon resumeChris Wilson1-1/+1
2019-12-31drm/i915/gt: Tweak flushes around ivb ppgttChris Wilson1-2/+2
2019-12-30drm/i915/gt: Do not restore invalid RS stateChris Wilson1-13/+11
2019-12-23drm/i915: Mark the GEM context link as RCU protectedChris Wilson1-1/+1
2019-12-22drm/i915/gt: Merge engine init/setup loopsChris Wilson1-15/+4
2019-12-22drm/i915/gt: Pull GT initialisation under intel_gt_init()Chris Wilson1-8/+6
2019-12-21drm/i915: Remove i915->kernel_contextChris Wilson1-1/+1
2019-12-20drm/i915: Drop GEM context as a direct link from i915_requestChris Wilson1-4/+4
2019-12-18drm/i915/gt: Remove direct invocation of breadcrumb signalingChris Wilson1-1/+1
2019-12-17drm/i915/gt: Avoid multi-LRI on SandybridgeChris Wilson1-4/+8
2019-12-17drm/i915/gt: Tidy up full-ppgtt on IvybridgeChris Wilson1-69/+41
2019-12-13drm/i915: Introduce new macros for tracingVenkata Sandeep Dhanalakota1-7/+6
2019-12-08drm/i915/gt: Turn vm off then on again for gen7 mm switchChris Wilson1-12/+10
2019-12-07drm/i915/gt: Replace I915_WRITE with its uncore counterpartAndi Shyti1-23/+25
2019-12-05drm/i915/gt: Bump the PP_DIR invalidation for BaytrailChris Wilson1-4/+35
2019-12-04drm/i915/gt: Set the PD again for HaswellChris Wilson1-35/+14
2019-12-03drm/i915/gt: Track the context validity explicitlyChris Wilson1-1/+3
2019-11-30drm/i915/gt: Push the flush_pd before the set-contextChris Wilson1-15/+13
2019-11-30drm/i915/gen7: Re-enable full-ppgtt for ivb & hswChris Wilson1-12/+9
2019-11-13drm/i915/gt: Invalidate as we write the gen7 breadcrumbChris Wilson1-6/+3
2019-11-12drm/i915/gt: Flush gen7 even harderChris Wilson1-2/+3
2019-11-12drm/i915/gt: Try an extra flush on the Haswell blitterChris Wilson1-1/+4
2019-10-24drm/i915/gt: Split intel_ring_submissionChris Wilson1-0/+2053
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-15 20:17:47 +0300