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path: root/drivers/gpu/drm/i915/gt/intel_gt_regs.h
AgeCommit message (Expand)AuthorFilesLines
2022-04-30drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidationMatt Roper1-0/+1
2022-04-21drm/i915/gsc: add gsc as a mei auxiliary deviceTomas Winkler1-0/+1
2022-04-21Merge drm/drm-next into drm-intel-gt-nextRodrigo Vivi1-1/+0
2022-04-19drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platformsUmesh Nerlige Ramappa1-0/+18
2022-04-11Merge drm/drm-next into drm-intel-nextJani Nikula1-34/+14
2022-04-06drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6()Ashutosh Dixit1-1/+0
2022-03-30drm/i915/dg2: Add Wa_22014226127José Roberto de Souza1-0/+1
2022-03-16drm/i915: Add support for steered register writesMatt Roper1-0/+1
2022-03-02drm/i915/xehp: Add compute workaroundsMatt Roper1-0/+1
2022-03-02drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODEMatt Roper1-0/+3
2022-03-02drm/i915: Move context descriptor fields to intel_lrc.hMatt Roper1-34/+0
2022-03-02drm/i915/xehp: Add Compute CS IRQ handlersMatt Roper1-0/+3
2022-03-02drm/i915/xehp: Define compute class and engineMatt Roper1-0/+4
2022-02-25drm/i915/dg2: add Wa_14014947963Clint Taylor1-0/+3
2022-02-23Merge tag 'drm-intel-gt-next-2022-02-17' of git://anongit.freedesktop.org/drm...Rodrigo Vivi1-0/+4
2022-02-16drm/i915: Move MCHBAR registers to their own headerMatt Roper1-7/+0
2022-02-16drm/i915/gt: Order GT registers by MMIO offsetMatt Roper1-1059/+1064
2022-02-16drm/i915/gt: Use consistent offset notation in intel_gt_regs.hMatt Roper1-103/+103
2022-02-16drm/i915/gt: Cleanup spacing of intel_gt_regs.hMatt Roper1-1069/+1069
2022-02-16drm/i915/gt: Use parameterized RING_MI_MODEMatt Roper1-8/+0
2022-02-16drm/i915/gt: Move SFC lock bits to intel_engine_regs.hMatt Roper1-19/+0
2022-02-16drm/i915/gt: Drop duplicate register definition for VDBOX_CGCTL3F18Matt Roper1-3/+0
2022-02-02drm/i915: Move [more] GT registers to their own header fileMatt Roper1-0/+11
2022-02-02drm/i915: Move GT registers to their own header fileMatt Roper1-0/+1543