summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_psr_regs.h
AgeCommit message (Expand)AuthorFilesLines
2025-06-02drm/i915/psr: Fix using wrong mask in REG_FIELD_PREPJouni Högander1-2/+2
2025-02-13drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registersJouni Högander1-0/+10
2024-10-23drm/i915/xe3lpd: Add new bit range of MAX swing setupSuraj Kandpal1-1/+1
2024-10-02drm/i915:Remove unused parameter in marcoHe Lugang1-2/+2
2024-09-11drm/i915/reg: fix transcoder timing register styleJani Nikula1-0/+1
2024-06-19intel_alpm: Fix wrong offset for PORT_ALPM_* registersJouni Högander1-2/+4
2024-05-23drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()Ville Syrjälä1-45/+0
2024-05-22drm/i915: Rename selective fetch plane registersVille Syrjälä1-5/+5
2024-05-22drm/i915: Simplify PIPESRC_ERLY_TPT definitionVille Syrjälä1-2/+2
2024-05-20drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wideJouni Högander1-0/+4
2024-05-06drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTLJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to PORT_ALPM_CTLJani Nikula1-1/+1
2024-05-06FIXME drm/i915: pass dev_priv explicitly to ALPM_CTL2Jani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to ALPM_CTLJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPTJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTLJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_SU_STATUSJani Nikula1-2/+2
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUSJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to PSR_EVENTJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_CTLJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUGJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNTJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_STATUSJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATAJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTLJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IIRJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IMRJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_CTLJani Nikula1-1/+1
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_EXITLINEJani Nikula1-1/+1
2024-04-25drm/i915: pass dev_priv to _MMIO_PIPE2, _MMIO_TRANS2, _MMIO_CURSOR2Jani Nikula1-19/+19
2024-04-02drm/i915/psr: Add missing ALPM AUX-Less register definitionsJouni Högander1-4/+8
2024-02-07drm/i915/alpm: Add ALPM register definitionsJouni Högander1-0/+57
2024-01-09drm/i915/psr: Enable psr2 early transport as possibleJouni Högander1-0/+1
2024-01-09drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transportJouni Högander1-0/+5
2023-11-07drm/i915/display: Support PSR entry VSC packet to be transmitted one frame ea...Mika Kahola1-0/+2
2023-06-16drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setupVille Syrjälä1-0/+12
2023-06-16drm/i915/psr: Reintroduce HSW PSR1 registersVille Syrjälä1-0/+4
2023-06-16drm/i915/psr: Fix BDW PSR AUX CH data register offsetsVille Syrjälä1-1/+1
2023-04-20drm/i915/psr: Define more PSR mask bitsVille Syrjälä1-2/+12
2023-04-20drm/i915/psr: Clean up PSR register defininitionsVille Syrjälä1-96/+101
2023-04-04drm/i915/psr: split out PSR regs to a separate fileJani Nikula1-0/+260
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-01 09:30:24 +0300