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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
AgeCommit message (Expand)AuthorFilesLines
2020-11-16drm: fix some kernel-doc markupsMauro Carvalho Chehab1-1/+1
2020-10-16drm/i915/dg1: Enable DPLL for DG1Lucas De Marchi1-4/+4
2020-10-16drm/i915/dg1: Add and setup DPLLs for DG1Aditya Swarup1-4/+38
2020-10-14drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay1-8/+8
2020-10-06drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clockImre Deak1-16/+25
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak1-0/+13
2020-09-16drm/i915/pll: Centralize PLL_ENABLE register lookupAnusha Srivatsa1-17/+18
2020-09-08Merge tag 'v5.9-rc4' into drm-nextDave Airlie1-4/+4
2020-08-24treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva1-4/+4
2020-08-17drm/i915/rkl: Handle HTIMatt Roper1-0/+11
2020-08-17drm/i915/rkl: Add DPLL4 supportMatt Roper1-5/+36
2020-07-01drm/i915/icl+: Simplify combo/TBT PLL calculation call-chainImre Deak1-37/+27
2020-07-01drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clockImre Deak1-1/+12
2020-04-21drm/i915/display/dpll_mgr: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya1-4/+4
2020-03-09drm/i915: Fix documentation for intel_dpll_get_freq()Imre Deak1-0/+7
2020-03-02drm/i915: Unify the DPLL ref clock frequency trackingImre Deak1-56/+119
2020-03-02drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out againImre Deak1-5/+2
2020-03-02drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculationImre Deak1-139/+130
2020-03-02drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculationImre Deak1-35/+56
2020-03-02drm/i915/hsw: Split out the SPLL parameter calculationImre Deak1-14/+22
2020-03-02drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLLImre Deak1-5/+5
2020-03-02drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding itImre Deak1-9/+12
2020-03-02drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak1-0/+418
2020-03-02drm/i915: Move the DPLL vfunc inits after the func definesImre Deak1-60/+60
2020-03-02drm/i915: Keep the global DPLL state in a DPLL specific structImre Deak1-30/+30
2020-03-02drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.cImre Deak1-0/+59
2020-03-02drm/i915: Fix bounds check in intel_get_shared_dpll_id()Imre Deak1-3/+6
2020-02-11drm/i915/dpll_mgr: convert to drm_device based logging macros.Wambui Karuga1-112/+142
2020-02-04drm/i915/display/dpll_mgr: Make WARN* drm specific where drm_device ptr is av...Pankaj Bharadiya1-18/+19
2020-01-27drm/i915/dpll_mgr: use intel_de_*() functions for register accessJani Nikula1-187/+201
2020-01-13drm/i915: Pass intel_encoder to enc_to_*()Ville Syrjälä1-2/+2
2019-11-01drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.Maarten Lankhorst1-10/+10
2019-10-25drm/i915: Fix PCH reference clock for FDI on HSW/BDWVille Syrjälä1-0/+15
2019-10-09drm/i915: Select DPLL's via maskMatt Roper1-22/+26
2019-10-04drm/i915/tgl: Add the Thunderbolt PLL divider valuesImre Deak1-2/+40
2019-09-27drm/i915/tgl: Fix dkl link trainingJosé Roberto de Souza1-7/+7
2019-09-25drm/i915/tgl: Add dkl phy pll calculationsJosé Roberto de Souza1-7/+38
2019-09-25drm/i915/tgl: re-indent code to prepare for DKL changesLucas De Marchi1-53/+66
2019-09-25drm/i915/tgl: Add support for dkl pll writeVandita Kulkarni1-1/+64
2019-09-25drm/i915/tgl: Add initial dkl pll supportLucas De Marchi1-2/+94
2019-09-23drm/i915/tgl/pll: Set update_active_dpllClinton A Taylor1-0/+1
2019-09-02drm/i915: Prefer encoder->name over port_name()Ville Syrjälä1-2/+2
2019-08-17drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio1-33/+11
2019-08-07drm/i915: rename intel_drv.h to display/intel_display_types.hJani Nikula1-1/+1
2019-07-18drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1Vivek Kasireddy1-4/+14
2019-07-12drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza1-2/+6
2019-07-12drm/i915/tgl: Add DPLL registersLucas De Marchi1-5/+19
2019-07-12drm/i915/tgl: Add pll managerVandita Kulkarni1-1/+18
2019-07-11drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä1-12/+7
2019-07-11drm/i915: Transition port type checks to phy checksMatt Roper1-5/+6
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