summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_dp.h
AgeCommit message (Expand)AuthorFilesLines
2023-11-21drm/i915/dp_mst: Fix PBN / MTP_TU size calculation for UHBR ratesImre Deak1-0/+2
2023-11-21drm/i915/dp: Fix UHBR link M/N valuesImre Deak1-0/+2
2023-11-21drm/i915/dp: Replace intel_dp_is_uhbr_rate() with drm_dp_is_uhbr_rate()Imre Deak1-1/+0
2023-11-08drm/i915: Query compressed bpp properly using correct DPCD and DP Spec infoStanislav Lisovskiy1-0/+4
2023-11-08drm/i915/dp_mst: Improve BW sharing between MST streamsImre Deak1-0/+3
2023-11-08drm/i915/dp: Enable DSC via the connector decompression AUXImre Deak1-3/+6
2023-11-08drm/i915/dp: Pass actual BW overhead to m_n calculationImre Deak1-0/+2
2023-11-08drm/i915/dp_mst: Enable FEC early once it's known DSC is neededImre Deak1-0/+5
2023-10-16drm/i915/dp: Remove unused DSC caps from intel_dpImre Deak1-2/+1
2023-10-16drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_get_slice_count()Imre Deak1-1/+1
2023-10-16drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_max_bpp()Imre Deak1-1/+2
2023-10-16drm/i915/dp_mst: Set connector DSC capabilities and decompression AUXImre Deak1-0/+3
2023-09-28drm/i915/dp: Update the link bpp limits for DSC modeImre Deak1-0/+6
2023-09-28drm/i915/dp: Track the pipe and link bpp limits separatelyImre Deak1-1/+8
2023-08-25drm/i915/display: configure SDP split for DP-MSTVinod Govindapillai1-0/+3
2023-08-18drm/i915/dp: Rename helper to get DSC max pipe_bppAnkit Nautiyal1-1/+1
2023-08-18drm/i915/dp: Use consistent name for link bpp and compressed bppAnkit Nautiyal1-7/+7
2023-08-18drm/i915/dp_mst: Use output_format to get the final link bppAnkit Nautiyal1-0/+1
2023-08-18drm/i915/dp: Consider output_format while computing dsc bppAnkit Nautiyal1-0/+1
2023-06-02drm/i915/dp: stop caching has_hdmi_sink in struct intel_dpJani Nikula1-0/+1
2023-05-16drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disc...Imre Deak1-0/+3
2022-12-13drm/i915: Bpp/timeslot calculation fixes for DP MST DSCStanislav Lisovskiy1-1/+2
2022-12-13drm/i915: Extract VESA DSC bpp alignment to separate functionStanislav Lisovskiy1-0/+1
2022-12-13drm/i915: Add DSC support to MST pathStanislav Lisovskiy1-0/+17
2022-09-06Revert "drm/i915: Add DSC support to MST path"Jani Nikula1-17/+0
2022-09-06drm/i915: Add DSC support to MST pathStanislav Lisovskiy1-0/+17
2022-05-27drm/i915/bios: Split VBT data into per-panel vs. global partsVille Syrjälä1-0/+1
2022-05-27drm/i915: Extract intel_edp_fixup_vbt_bpp()Ville Syrjälä1-0/+1
2022-02-02drm/i915: Only include i915_reg.h from .c filesMatt Roper1-2/+0
2021-12-01drm/i915/dp: Perform 30ms delay after source OUI writeLyude Paul1-0/+2
2021-09-30drm/i915: Enable TPS3/4 on all platforms that support themVille Syrjälä1-2/+2
2021-09-23drm/i915/display: Only keep PSR enabled if there is active planesJosé Roberto de Souza1-1/+1
2021-09-20drm/i915/dp: add helper for checking for UHBR link rateJani Nikula1-0/+1
2021-08-30drm/i915/display: Move DRRS code its own fileJosé Roberto de Souza1-11/+0
2021-08-24drm/i915/dp: add max data rate calculation for UHBR ratesJani Nikula1-1/+1
2021-08-24drm/i915/dp: use actual link rate values in struct link_config_limitsJani Nikula1-1/+1
2021-04-28drm/i915/hdcp: add intel_dp_hdcp.h and rename init accordinglyJani Nikula1-3/+0
2021-03-19drm/i915: Introduce g4x_dp.cVille Syrjälä1-6/+0
2021-03-19drm/i915: Split intel_ddi_encoder_reset() from intel_dp_encoder_reset()Ville Syrjälä1-1/+0
2021-03-19drm/i915: Relocate intel_dp_program_link_training_pattern()Ville Syrjälä1-4/+0
2021-01-21drm/i915/dp: split out aux functionality to intel_dp_aux.cJani Nikula1-1/+0
2021-01-19drm/i915: Fix the PHY compliance test vs. hotplug mishapVille Syrjälä1-0/+1
2021-01-14drm/i915/pps: abstract panel power sequencer from intel_dp.cJani Nikula1-4/+1
2021-01-13drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.cImre Deak1-3/+0
2020-12-22drm/i915/display: Let PCON convert from RGB to YCbCr if it canAnkit Nautiyal1-1/+2
2020-12-22drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encodingAnkit Nautiyal1-0/+2
2020-12-22drm/i915: Add support for starting FRL training for HDMI2.1 via PCONAnkit Nautiyal1-0/+2
2020-11-18drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.Maarten Lankhorst1-0/+1
2020-10-20drm/i915: s/intel_dp_sink_dpms/intel_dp_set_power/Ville Syrjälä1-1/+1
2020-10-12drm/i915: Switch to LTTPR non-transparent mode link trainingImre Deak1-2/+0
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-12 15:14:28 +0300