summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.c
AgeCommit message (Expand)AuthorFilesLines
2023-06-05drm/i915/mtl: Reset only one lane in case of MFDMika Kahola1-16/+23
2023-05-19drm/i915/hdmi: C20 computed PLL frequenciesClint Taylor1-6/+84
2023-05-18drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disablingMika Kahola1-3/+1
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula1-5/+5
2023-04-29drm/i915/mtl: Power up TCSSMika Kahola1-0/+19
2023-04-29drm/i915/mtl: Readout Thunderbolt HW stateMika Kahola1-0/+27
2023-04-29drm/i915/mtl: Enabling/disabling sequence Thunderbolt pllMika Kahola1-3/+132
2023-04-29drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLAMika Kahola1-2/+5
2023-04-29drm/i915/mtl: C20 port clock calculationMika Kahola1-0/+45
2023-04-29drm/i915/mtl: Dump C20 pll hw stateMika Kahola1-0/+20
2023-04-29drm/i915/mtl: C20 HW readoutMika Kahola1-12/+612
2023-04-29drm/i915/mtl: C20 PLL programmingMika Kahola1-38/+250
2023-04-15drm/i915: Make intel_{mpllb,c10pll}_state_verify() saferVille Syrjälä1-0/+5
2023-04-14drm/i915/mtl: Add C10 phy programming for HDMIRadhakrishna Sripada1-3/+607
2023-04-14drm/i915/mtl: Add vswing programming for C10 physMika Kahola1-5/+97
2023-04-14drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada1-0/+1207
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-19 13:13:52 +0300