summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/include
AgeCommit message (Expand)AuthorFilesLines
2020-11-10Merge tag 'amd-drm-next-5.11-2020-11-05' of git://people.freedesktop.org/~agd...Dave Airlie20-3/+269167
2020-11-05drm/amdgpu: Add GFX Fine Grain Clock Gating flagJinzhou.Su1-0/+1
2020-10-30drm/amdgpu: drop CONFIG_DRM_AMD_DC_DCN3_01 from atomfirmware.hAlex Deucher1-4/+0
2020-10-27drm/amdgpu: add vangogh apu flagHuang Rui1-0/+1
2020-10-27drm/amd/pm: correct VR shared rail infoEvan Quan1-1/+3
2020-10-27drm/amd/pm: add edc leakage controller settingEvan Quan1-0/+16
2020-10-23drm/amdgpu: add GC 10.3 NOALLOC registersAlex Deucher3-0/+36
2020-10-15Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drmLinus Torvalds17-33/+577
2020-10-15drm/amdgpu: add missing newline at eofTom Rix1-1/+1
2020-10-12drm/amdgpu: initialize IP offset for dimgrey_cavefishTao Zhou1-0/+1049
2020-10-12Merge tag 'x86_pasid_for_5.10' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds1-1/+1
2020-10-07drm/amdgpu: add Green_Sardine APU flagAlex Deucher1-0/+1
2020-10-05drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tablesRoman Li1-1/+61
2020-10-05drm/amdgpu: update new memory types in atomfirmware headerHuang Rui1-0/+5
2020-10-05drm/amdgpu: add vangogh_reg_base_init function for van goghHuang Rui1-0/+1516
2020-10-05drm/amdgpu: add vangogh asic header files (v2)Huang Rui11-0/+266481
2020-09-30drm/amd/amdgpu: Define and implement a function that collects number ofRamesh Errabolu1-0/+12
2020-09-29drm/amd/powerplay: add one sysfs file to support the feature to modify gfx cl...Xiaojian Du1-0/+1
2020-09-25drm/include: add PP_FEATURE_MASK comments (v3)Ryan Taylor1-0/+28
2020-09-23drm/amdgpu: Add initial kernel documentation for the amd_ip_block_type struct...Ryan Taylor1-25/+62
2020-09-23drm/amdgpu: update athub interrupt harvesting handleStanley.Yang1-1/+3
2020-09-18drm/amdgpu: add VCN 3.0 AV1 registersAlex Deucher1-0/+34
2020-09-18drm/amdgpu: add the GC 10.3 VRS registersAlex Deucher3-0/+56
2020-09-18drm/amdgpu: add VCN 3.0 AV1 registersAlex Deucher1-0/+34
2020-09-18drm/amdgpu: add the GC 10.3 VRS registersAlex Deucher3-0/+56
2020-09-18drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700Tom St Denis2-0/+23
2020-09-17drm, iommu: Change type of pasid to u32Fenghua Yu1-1/+1
2020-08-26drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handlingAlex Deucher1-2/+0
2020-08-26drm/amdkfd: call amdgpu_amdkfd_get_hive_id directlyFelix Kuehling1-3/+0
2020-08-26drm/amdkfd: call amdgpu_amdkfd_get_unique_id directlyFelix Kuehling1-4/+0
2020-08-24drm/amd/display: remove unintended executable modeLukas Bulwahn4-0/+0
2020-08-17drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3Bhawanpreet Lakha1-0/+22
2020-08-06drm/amd/display: Read VBIOS Golden Settings TblIgor Kravchenko1-1/+53
2020-08-06drm/amd/powerplay: add new sysfs interface for retrieving gpu metrics(V2)Evan Quan1-0/+1
2020-08-06drm/amd/powerplay: define an universal data structure for gpu metrics (V4)Evan Quan1-0/+108
2020-08-05drm/amd/display: Read VBIOS Golden Settings TblIgor Kravchenko1-1/+53
2020-07-27drm/amdgpu: add some required DCE6 registers (v7)Alex Deucher2-0/+180
2020-07-27drm/amdgpu: add umc v8_7_0 IP headersJohn Clements2-0/+112
2020-07-27drm/amd/amdgpu: Add RLC_CGTT_MGCG_OVERRIDE to gfx 10.3 headersTom St Denis2-0/+27
2020-07-02drm/amdgpu/atomfirmware: update to latest integratedinfotableAlex Deucher1-0/+78
2020-07-01drm amdgpu: SI UVD registersSonny Jiang2-0/+902
2020-07-01drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)Tom St Denis2-4/+4
2020-07-01drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registersTom St Denis5-13/+26
2020-07-01drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bitsTom St Denis10-5/+109
2020-07-01drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)Tom St Denis10-0/+59
2020-07-01drm/amd/powerplay: and smc dpm info struct for sienna_cichlidLikun Gao1-0/+123
2020-07-01drm/amdgpu: add firmware_info v3_4 structure for Sienna_CichlidHawking Zhang1-0/+36
2020-07-01drm/amdgpu: add vram_info v2_5 in atomfirmware headerHawking Zhang1-0/+124
2020-06-03drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlidLikun Gao1-0/+1
2020-06-03drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2)Likun Gao2-0/+90
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 19:06:26 +0300