summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/include/asic_reg/gc
AgeCommit message (Expand)AuthorFilesLines
2025-03-07drm/amdkfd: Add support for more per-process flagHarish Kasiviswanathan1-0/+2
2025-03-07drm/amd/amdgpu: Add missing GC 11.5.0 registerTom St Denis1-0/+2
2024-06-05drm/amdgpu: update gc_12_0_0 headersAlex Deucher2-0/+106
2024-05-23drm/amdgpu: Add missing offsets in gc_11_0_0_offset.hSunil Khatri1-0/+10
2024-04-30drm/amdgpu: Add gc v12_0_0 ip headers (v4)Hawking Zhang2-0/+51505
2024-04-27drm/amdgpu: add support of gfx10 register dumpSunil Khatri1-0/+12
2024-03-20drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUSTao Zhou1-0/+4
2023-11-30drm/amdgpu: Force order between a read and write to the same addressAlex Sierra1-0/+2
2023-10-20drm/amdgpu: update to the latest GC 11.5 headersAlex Deucher1-0/+48
2023-08-30drm/amdgpu: add gc headers for gc 11.5.0Lang Yu2-0/+46531
2023-06-09drm/amdgpu: setup hw debug registers on driver initializationJonathan Kim5-0/+101
2023-06-09drm/amdgpu: Add gc v9_4_3 ras error status registersHawking Zhang2-0/+1304
2023-03-31drm/amdgpu: add gc v9_4_3 ip headersHawking Zhang2-0/+37793
2023-03-14drm/amd/amdgpu: Add missing INT_STAT_DEBUG registers to GC 10.1 and 10.3 headersTom St Denis4-0/+116
2023-01-18amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headersYiPeng Chai2-0/+58
2022-09-13drm/amd/amdgpu: update GC 10.3.0 pwrdecTom St Denis2-1/+1558
2022-09-08drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headersTom St Denis2-0/+14
2022-08-30drm/amdgpu: add gc v11_0_3 ip headersFrank Min2-0/+56726
2022-08-17drm/amdgpu: save and restore gc hub regsVictor Zhao1-0/+4
2022-07-28drm/amd/amdgpu: add additional page fault settings for gfx11Chengming Gui2-0/+28
2022-04-29drm/amdgpu: add gc v11_0_0 ip headers v11Hawking Zhang3-0/+59419
2021-08-06drm/amd/amdgpu: add regCP_MEx_INT_STAT_DEBUG for Aldebaran debuggingTom St Denis2-0/+58
2021-04-21drm/amdgpu: only harvest gcea/mmea error status in arcturusHawking Zhang1-0/+16
2021-04-09drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headersTom St Denis2-0/+15
2021-03-10drm/amdgpu: add gc v9_4_2 ip headers (v3)Hawking Zhang2-0/+40632
2020-10-23drm/amdgpu: add GC 10.3 NOALLOC registersAlex Deucher3-0/+36
2020-10-15drm/amdgpu: add missing newline at eofTom Rix1-1/+1
2020-09-23drm/amdgpu: update athub interrupt harvesting handleStanley.Yang1-1/+3
2020-09-18drm/amdgpu: add the GC 10.3 VRS registersAlex Deucher3-0/+56
2020-07-27drm/amd/amdgpu: Add RLC_CGTT_MGCG_OVERRIDE to gfx 10.3 headersTom St Denis2-0/+27
2020-07-01drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)Tom St Denis2-4/+4
2020-07-01drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registersTom St Denis5-13/+26
2020-07-01drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bitsTom St Denis10-5/+109
2020-07-01drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)Tom St Denis10-0/+59
2020-06-03drm/amdgpu: add GC 10.3 header files (v2)Likun Gao3-0/+68433
2020-05-12drm/amd/amdgpu: Add missing GRBM bits for GFX 10.1Tom St Denis1-0/+4
2020-04-01drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own headerTom St Denis2-7/+0
2020-04-01drm/amd/amdgpu: Add GFX9.1 PWR_MISC_CNTL_STATUS register to headersTom St Denis2-0/+7
2020-01-31drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for ArcturusJoseph Greathouse1-2/+4
2020-01-23drm/amdgpu: add EDC counter registers of gc for ArcturusDennis Li2-0/+1012
2020-01-14drm/amdgpu: add defines for DF and TCP HashingJoseph Greathouse1-0/+6
2019-12-23drm/amdgpu: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support ArcturusJames Zhu1-0/+8
2019-10-15drm/amd/include: add register define for VML2 and ATCL2Dennis Li2-4/+32
2019-08-02drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan2-0/+41
2019-07-31drm/amd/include: add define of TCP_EDC_CNT_NEWDennis Li1-0/+2
2019-07-31drm/amd/include: add bitfield define for EDC registersDennis Li1-0/+157
2019-06-20drm/amdgpu: add GC 10.1 register headers (v4)Hawking Zhang3-0/+61330
2019-05-24drm/amdgpu: add EDC counter registerJames Zhu1-0/+31
2018-10-10drm/amdgpu: add CP_DEBUG register definition for GC9.0Tao Zhou1-0/+2
2018-09-11drm/amd/include: update the bitfield define for PF_MAX_REGIONShaoyun Liu1-2/+2
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-21 09:08:39 +0300